參數(shù)資料
型號： MC74HC390DR2
廠商： ON SEMICONDUCTOR
元件分類： 計數(shù)器
英文描述： HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDSO16
封裝： PLASTIC, SOIC-16
文件頁數(shù)： 3/9頁
文件大小： 223K
代理商： MC74HC390DR2
MC74HC390
http://onsemi.com
3
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C
v 125_C
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)
2.0
4.5
6.0
5.4
27
32
4.4
22
26
3.6
18
21
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock A to QA
(Figures 1 and 3)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock A to QC
(QA connected to Clock B)
(Figures 1 and 3)
2.0
4.5
6.0
290
58
49
365
73
62
435
87
74
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock B to QB
(Figures 1 and 3)
2.0
4.5
6.0
130
26
22
165
33
28
195
39
33
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock B to QC
(Figures 1 and 3)
2.0
4.5
6.0
185
37
31
230
46
39
280
56
48
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock B to QD
(Figures 1 and 3)
2.0
4.5
6.0
130
26
22
165
33
28
195
39
33
ns
tPHL
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
2.0
4.5
6.0
165
33
28
205
41
35
250
50
43
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
—
10
10
10
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Counter)*
Typical @ 25°C, VCC = 5.0 V
pF
35
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C
v 125_C
trec
Minimum Recovery Time, Reset Inactive to Clock A or Clock B
(Figure 2)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
tw
Minimum Pulse Width, Clock A, Clock B
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tf, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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