參數(shù)資料
型號: MC74HC242
廠商: Motorola, Inc.
英文描述: Quad 3-State Bus Transceiver
中文描述: 四三態(tài)總線收發(fā)器
文件頁數(shù): 1/5頁
文件大?。?/td> 119K
代理商: MC74HC242
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC74HC242 is identical in pinout to the LS242. The device inputs
are compatible with Standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
This quad bus transceiver is designed for asynchronous two–way
communications between data buses. The states of the Output Enables
(A–to–B Enable and B–to–A Enable) determine both the direction of data
flow (from A to B or from B to A) and the modes of the Data Ports (input,
output, or high–impedance).
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 130 FETs or 32.5 Equivalent Gates
LOGIC DIAGRAM
Pin 14 = VCC
Pin 7 = GND
Pins 2, 12 = No Connection
A1
3
Output
EnableS
B Data
Port
A2
4
A3
5
A4
6
A–TO–B ENABLE
1
B–TO–A ENABLE
13
B1
11
B2
10
B3
9
B4
8
A Data
Port
Pinout: 14–Lead Plastic Package
(Top View)
13
14
12
11
10
9
8
2
1
3
4
5
6
7
VCC
B–to–A
Enable
NC
B1
B2
B3
B4
A–to–B
Enable
NC
A1
A2
A3
A4
GND
NC = No Connection
H
L
H
L
H
H
L
L
O
Z
Z
I
I
Z
Z
O
I = Input; O = Output, O = Inverting Output
Z = High Impedance
FUNCTION TABLE
Control Inputs
Data Port Status
A–to–B
Enable
B–to–A
Enable
A
B
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
1
14
ORDERING INFORMATION
MC74HCXXXN
Plastic
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