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參數(shù)資料
| 型號(hào)： | MC74HC195N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-Bit Universal Shift Register |
| 中文描述： | HC/UH SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 203K |
| 代理商： | MC74HC195N |
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 6
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC74HC195 is identical in pinout to the LS195. The device inputs are
compatible with standard CMOS outputs, with pull up resistors, they are
compatible with LSTTL outputs.
This static shift register features parallel load, serial load (shift right), hold,
and reset modes of operation. These modes are tabulated in the Function
Table, and further explanation can be found in the Pin Description section.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 150 FETs or 37.5 Equivalent Gates
LOGIC DIAGRAM
PIN 16 = VCC
PIN 8 = GND
2
3
4
5
6
7
10
9
1
15
14
12
11
J
K
A
B
C
D
CLOCK
SERIAL SHIFT/
PARALLEL LOAD
RESET
QA
QB
QC
QD
QD
SERIAL DATA
INPUTS
PARALLEL
DATA
INPUTS
PARALLEL
DATA
OUTPUTS
FUNCTION TABLE
Inputs
Serial
Outputs
Operating Mode
Parallel
Reset
Shift/
Load
Clock
J
K
A
B
C
D
QA
L
QB
L
QC
L
QD
L
QD
H
L
X
X
X
X
X
X
X
X
Reset
H
L
X
X
a
b
c
d
a
b
c
d
d
Parallel Load
H
H
L
X
X
X
X
X
X
No Change
Hold
H
H
H
H
H
H
H
H
L
L
H
H
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
QA0
L
H
QAn
QA0
QAn
QAn
QAn
QA0 = the level of QA before the indicated steady–state
input conditions were established.
QAn, QBn, QCn = the level of QA, QB, or QC,
respectively, before the most recent
of the clock.
QBn
QBn
QBn
QBn
QCn
QCn
QCn
QCn
QCn
QCn
QCn
QCn
Retain First Stage
Reset First Stage
Set First Stage
Toggle First Stage
Serial
Shift
H = high level (steady state)
L = low level (steady state)
X = don’t care
= transition from low to high level.
a, b, c, d = the level of steady–state input at inputs
A, B, C, or D, respectively.
transition
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
QD
QC
QB
QA
VCC
SERIAL SHIFT/
PARALLEL LOAD
CLOCK
QD
A
K
J
RESET
GND
D
C
B
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
1
16
ORDERING INFORMATION
MC74HCXXXN
Plastic
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