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參數(shù)資料
| 型號： | MC74HC194 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4-Bit Bidirectional Universal Shift Register |
| 中文描述： | 4位雙向通用移位寄存器 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 211K |
| 代理商： | MC74HC194 |
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC74HC194 is identical in pinout to the LS194 and the MC14194B
metal gate CMOS device. The device inputs are compatible with standard
CMOS outputs; with pull–up resistors, they are compatible with LSTTL
outputs.
This static shift register features parallel load, serial load (shift right and
shift left), hold, and reset modes of operation. These modes are tabulated in
the Function Table, and further explanation can be found in the Pin
Description section.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity 164 FETs or 41 Equivalent Gates
FUNCTION TABLE
Inputs
Serial
Data
Outputs
QB
L
Mode
Reset
Mode
Select
Clock
Parallel Data
B
Operating
S1
S0
SD
X
SA
X
A
C
D
QA
L
QC
L
QD
L
L
X
X
X
X
X
X
X
Reset
H
H
H
X
X
a
b
c
d
a
b
c
d
Parallel Load
H
H
L
L
H
H
X
X
H
L
X
X
X
X
X
X
X
X
H
L
QAn
QAn
QCn
QCn
No Change
No Change
No Change
QBn
QBn
QDn
QDn
QCn
QCn
H
L
Shift Right
H
H
H
H
L
L
H
L
X
X
X
X
X
X
X
X
X
X
QBn
QBn
Shift Left
H
H
H
L
X
X
L
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Hold
H = high level (steady state)
L = low level (steady state)
X = don’t care
= transition from low to high level.
a, b, c, d = the level of steady–state input at inputs A, B, C, or D, respectively.
QAn, QBn, QCn, QDn = the level of QA, QB, QC, or QD, respectively, before
the most recent
transition of the clock.
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
QD
QC
QB
QA
VCC
S0
S1
CLOCK
B
A
SA
RESET
GND
D
C
SD
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
1
16
ORDERING INFORMATION
MC74HCXXXN
Plastic
LOGIC DIAGRAM
15
14
SERIAL
DATA
INPUTS
PARALLEL
DATA
INPUTS
MODE
SELECT
SA
SD
A
B
C
D
CLOCK
S1
S0
RESET
PARALLEL
DATA
OUTPUTS
QA
QB
QC
QD
13
12
10
9
1
11
6
5
4
3
7
2
VCC = PIN 16
GND = PIN 8
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相關代理商/技術參數(shù) |
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