參數(shù)資料
型號: MC74HC165AD
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: 8-Bit Serial or Parallel-Input/Serial-Output Shift Register
中文描述: HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDSO16
封裝: 0.150 INCH, PLASTIC, SOIC-16
文件頁數(shù): 4/9頁
文件大?。?/td> 280K
代理商: MC74HC165AD
MC54/74HC165A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
4
Symbol
Parameter
V
25 C
85 C
2.0
6.0
13
Unit
tsu
Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load
75
95
16
125 C
110
19
tsu
Minimum Setup Time, Input SA to Clock (or Clock Inhibit)
2.0
6.0
75
13
95
16
110
19
ns
tsu
Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
4.5
15
19
22
ns
4.5
1
1
1
(Figure 5)
3.0
4.5
1
1
1
1
1
1
(Figure 6)
3.0
1
1
1
(Figure 7)
3.0
30
40
55
Minimum Pulse Width, Clock (or Clock Inhibit)
(Figure 1)
2.0
3.0
6.0
70
27
13
90
32
16
100
36
19
tw
Minimum Pulse width, Serial Shift/Parallel Load
2.0
6.0
70
13
90
16
100
19
ns
tr, tf
Maximum Input Rise and Fall Times
2.0
6.0
1000
400
1000
400
1000
400
ns
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ns
相關PDF資料
PDF描述
MC74HC165AN 8-Bit Serial or Parallel-Input/Serial-Output Shift Register
MC74HC165D 8-Bit Serial or Parallel-Input/Serial-Output Shift Register
MC74HC165N 8-Bit Serial or Parallel-Input/Serial-Output Shift Register
MC74HC173D Quad 3-State D Flip-Flop with Common Clock and Reset
MC74HC173N Quad 3-State D Flip-Flop with Common Clock and Reset
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