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參數(shù)資料
| 型號(hào)： | MC74HC161AN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | PRESETTABLE COUNTERS HIGH-PERFORMANCE SILICON-GATE CMOS |
| 中文描述： | HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 284K |
| 代理商： | MC74HC161AN |
M
h
1
P0
P1
P2
P3
ENABLE P
ENABLE T
RESET
T0
R
C
C
LOAD
LOAD
P0
Q0
Q0
Q1
Q2
Q3
RIPPLE
CARRY
OUT
VCC= PIN 16
GND = PIN 8
14
The flip–flops shown in the circuit diagrams are Toggle–Enable flip–flops. A Toggle–
Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data from
Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flip–flop. The logic level at the Pn input is then clocked to the Q output of the flip–flop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
output of the flip–flop low.
Q0
Q1
Q1
Q2
Q2
Q3
T1
R
C
C
LOAD
LOAD
P1
T2
R
C
C
LOAD
LOAD
P2
T3
R
C
C
LOAD
LOAD
P3
13
12
11
15
3
4
5
6
7
10
1
9
2
R
C
C
LOAD
LOAD
CLOCK
LOAD
F
(
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