參數(shù)資料
型號: MC74HC161AN
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: PRESETTABLE COUNTERS HIGH-PERFORMANCE SILICON-GATE CMOS
中文描述: HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 1/16頁
文件大小: 284K
代理商: MC74HC161AN
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 8
1
Publication Order Number:
MC74HC161A/D
High–Performance Silicon–Gate CMOS
The MC74HC161A and HC163A are identical in pinout to the
LS161 and LS163. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC161A and HC163A are programmable 4–bit binary counters
with asynchronous and synchronous reset, respectively.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 192 FETs or 48 Equivalent Gates
HC161A
Binary
Mode
Asynchronous
Reset Mode
LOGIC DIAGRAM
PIN 16 = VCC
PIN 8 = GND
11
12
13
14
Q0
Q1
Q2
Q3
15
RIPPLE
CARRY
OUT
BCD OR
BINARY
OUTPUT
3
4
5
6
P0
P1
P2
P3
2
CLOCK
RESET
LOAD
ENABLE P
ENABLE T
COUNT
ENABLES
PRESET
DATA
INPUTS
1
9
7
10
Inputs
Load
Output
Q
Clock
Reset*
Enable P
Enable T
L
H
H
H
H
X
L
H
H
H
X
X
H
L
X
X
X
H
X
L
Reset
Load Preset Data
Count
No Count
No Count
FUNCTION TABLE
*HC163A only. HC161A is an Asynchronous Reset Device
H = high level, L = low level, X = don’t care
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
RESET
P0
CLOCK
GND
Q1
Q0
RIPPLE
CARRY OUT
VCC
P1
P2
P3
ENABLE P
Q2
Q3
ENABLE T
LOAD
SO–16
D SUFFIX
CASE 751B
http://onsemi.com
1
16
PDIP–16
N SUFFIX
CASE 648
1
16
MARKING
DIAGRAMS
16
1
16
MC74HC16xAN
AWLYYWW
1
HC16xA
AWLYWW
A
WL = Wafer Lot
YY
= Year
WW = Work Week
= Assembly Location
Device
Package
Shipping
ORDERING INFORMATION
MC74HC16xAN
PDIP–16
2000 / Box
MC74HC16xAD
SOIC–16
48 / Rail
MC74HC16xADR2
SOIC–16
2500 / Reel
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