參數(shù)資料
型號(hào): MC74HC126AN
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Quad 3-State Noninverting Buffers
中文描述: HC/UH SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDIP14
封裝: PLASTIC, DIP-14
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 171K
代理商: MC74HC126AN
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 9
1
Publication Order Number:
MC74HC125A/D
High–Performance Silicon–Gate CMOS
The MC74HC125A and MC74HC126A are identical in pinout to
the LS125 and LS126. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be
used with 3–state memory address drivers, clock drivers, and other
bus–oriented systems. The devices have four separate output enables
that are active–low (HC125A) or active–high (HC126A).
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 72 FETs or 18 Equivalent Gates
LOGIC DIAGRAM
HC125A
Active–Low Output Enables
HC126A
Active–High Output Enables
Y1
Y2
Y4
3
6
8
11
13
12
10
9
4
5
1
2
A1
OE1
A2
OE2
A3
OE3
A4
OE4
PIN 14 = VCC
PIN 7 = GND
FUNCTION TABLE
A1
OE1
A2
OE2
A3
OE3
A4
OE4
Y3
Y1
Y2
Y4
Y3
13
12
10
9
4
5
1
2
3
6
8
11
HC125A
Inputs
A
OE
Output
Y
H
L
X
L
L
H
H
L
Z
HC126A
Inputs
A
OE
Output
Y
H
L
X
H
H
L
H
L
Z
Device
Package
Shipping
ORDERING INFORMATION
MC74HC12xAN
PDIP–14
2000 / Box
MC74HC12xAD
SOIC–14
http://onsemi.com
55 / Rail
MC74HC12xADR2
SOIC–14
2500 / Reel
MARKING
DIAGRAMS
14
A
WL or L
YY or Y
WW or W = Work Week
= Assembly Location
= Wafer Lot
= Year
MC74HC12xADT
TSSOP–14
96 / Rail
MC74HC12xADTR2
TSSOP–14
2500 / Reel
TSSOP–14
DT SUFFIX
CASE 948G
HC
12xA
ALYW
1
14
1
PDIP–14
N SUFFIX
CASE 646
MC74HC12xAN
AWLYYWW
SOIC–14
D SUFFIX
CASE 751A
1
14
HC12xA
AWLYWW
PIN ASSIGNMENT
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OE3
Y4
A4
OE4
VCC
Y3
A3
OE2
Y1
A1
OE1
GND
Y2
A2
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