參數(shù)資料
型號: MC74HC138AD
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: CAP .27UF 200V B SERIES POLY
中文描述: HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16
封裝: SOIC-16
文件頁數(shù): 1/8頁
文件大?。?/td> 185K
代理商: MC74HC138AD
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 7
1
Publication Order Number:
MC74HC138A/D
High–Performance Silicon–Gate CMOS
The MC74HC138A is identical in pinout to the LS138. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC138A decodes a three–bit Address to one–of–eight
active–low outputs. This device features three Chip Select inputs, two
active–low and one active–high to facilitate the demultiplexing,
cascading, and chip–selecting functions. The demultiplexing function
is accomplished by using the Address inputs to select the desired
device output; one of the Chip Selects is used as a data input while the
other Chip Selects are held in their active states.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 100 FETs or 29 Equivalent Gates
LOGIC DIAGRAM
7
Y6
Y7
Y5
Y4
Y3
Y2
Y1
Y0
9
10
11
12
13
14
15
3
2
1
CS1
CS2
A0
A1
A2
ACTIVE–LOW
OUTPUTS
ADDRESS
INPUTS
CS3
CHIP–
SELECT
INPUTS
5
4
6
PIN 16 = VCC
PIN 8 = GND
Inputs
Outputs
CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
X
L
H
H
H
H
H
H
H
H
X
H
X
L
L
L
L
L
L
L
L
H
X
X
L
L
L
L
L
L
L
L
X
X
X
L
L
L
L
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
X
X
X
L
H
L
H
L
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
FUNCTION TABLE
H = high level (steady state); L = low level (steady state); X = don’t care
SO–16
D SUFFIX
CASE 751B
http://onsemi.com
TSSOP–16
DT SUFFIX
CASE 948F
1
16
PDIP–16
N SUFFIX
CASE 648
1
16
1
16
MARKING
DIAGRAMS
16
1
16
MC74HC138AN
AWLYYWW
1
HC138A
AWLYWW
A
WL = Wafer Lot
YY
= Year
WW = Work Week
= Assembly Location
HC
138A
ALYW
1
16
Device
Package
Shipping
ORDERING INFORMATION
MC74HC138AN
PDIP–16
2000 / Box
MC74HC138AD
SOIC–16
48 / Rail
MC74HC138ADR2
SOIC–16
2500 / Reel
MC74HC138ADT
TSSOP–16
96 / Rail
MC74HC138ADTR2
TSSOP–16
2500 / Reel
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
A0
CS2
A2
A1
Y7
CS1
CS3
GND
Y3
Y2
Y1
Y0
VCC
Y5
Y4
Y6
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