
MOTOROLA
MPC7457 RISC Microprocessor Hardware Specifications
51
System Design Information
1.9.2
PLL Power Supply Filtering
The AVDD power signal is provided on the MPC7457 to provide power to the clock generation PLL. To
ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any
noise in the 500 kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in
Figure 22 using surface mount capacitors with minimum effective series inductance (ESL) is recommended.
The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby
circuits. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery
of the 360 CBGA footprint and very close to the periphery of the 483 CBGA footprint, without the
inductance of vias.
The PLL power supply filter previously provided in the MPC7457 RISC Microprocessor Hardware
Specifications has been found to be less effective for Rev 1.1 devices with the low core voltages described
in this specification. As a result, the recommended value for the resistor in the circuit is being evaluated and
a new recommendation is indicated in
Figure 24. If the value indicated is not available, the nearest standard
value resistor may be used instead; a higher resistor value is recommended over a lower one. Motorola
continues to evaluate the filtering requirements of the MPC7457 and plans to make updated
recommendations as needed. Note that this recommendation applies to Rev. 1.1 devices only.
Figure 24. PLL Power Supply Filter Circuit
1.9.3
Decoupling Recommendations
Due to the MPC7457 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC7457 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC7457 system, and the MPC7457 itself requires a clean, tightly regulated source of
power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each
VDD, OVDD, and GVDD pin of the MPC7457. It is also recommended that these decoupling capacitors
receive their power from separate VDD, OVDD/GVDD, and GND power planes in the PCB, utilizing short
traces to minimize inductance.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic surface mount technology (SMT)
capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where
connections are made along the length of the part. Consistent with the recommendations of Dr. Howard
Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to
previous recommendations for decoupling Motorola microprocessors, multiple small capacitors of equal
value are recommended over using multiple values of capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, GVDD, and OVDD planes, to enable quick recharging of the smaller chip capacitors. These
bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response time
necessary. They should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors: 100–330 F (AVX TPS tantalum or Sanyo OSCON).
VDD
AVDD
400
2.2 F
GND
Low ESL Surface Mount Capacitors