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      參數(shù)資料
      型號: MC7447RX1267LB
      廠商: MOTOROLA INC
      元件分類: 微控制器/微處理器
      英文描述: 32-BIT, 1267 MHz, RISC PROCESSOR, CBGA360
      封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, FLIP CHIP, BGA-360
      文件頁數(shù): 16/87頁
      文件大?。?/td> 1586K
      代理商: MC7447RX1267LB
      MOTOROLA
      MPC7457 RISC Microprocessor Hardware Specifications
      23
      Electrical and Thermal Characteristics
      1.5.2.4.2
      L3 Bus AC Specifications for DDR MSUG2 SRAMs
      When using DDR MSUG2 SRAMs at the L3 interface, the parts should be connected as shown in Figure 9.
      Outputs from the MPC7457 are actually launched on the edges of an internal clock phase-aligned to
      SYSCLK (adjusted for core and L3 frequency divisors). L3_CLK0 and L3_CLK1 are this internal clock
      output with 90° phase delay, so outputs are shown synchronous to L3_CLK0 and L3_CLK1. Output valid
      Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing
      At recommended operating conditions. See Table 4.
      Field name1
      Affected
      Signals
      Value
      Output Valid Time
      Output Hold Time
      Unit
      Note
      s
      Parameter
      Symbol 2
      Change 3
      Parameter
      Symbol 2
      Change 3
      L3AOH
      L3_ADDR[18:0],
      L3_CNTL[0:1]
      0b00
      tL3CHOV
      0tL3CHOX
      0ps
      4
      0b01
      +50
      0b10
      +100
      0b11
      +150
      L3CLKn_OH
      All signals
      latched by
      SRAM
      connected to
      L3_CLKn
      0b000
      tL3CHOV,
      tL3CHDV,
      tL3CLDV
      0tL3CHOX,
      tL3CHDX,
      tL3CLDX,
      04
      0b001
      – 50
      5
      0b010
      – 100
      5
      0b011
      – 150
      5
      0b100
      – 200
      5
      0b101
      – 250
      5
      0b110
      – 300
      5
      0b111
      – 350
      5
      L3DOHn
      L3_DATA[n:n+7]
      , L3_DP[n/8]
      0b000
      tL3CHDV,
      tL3CLDV
      0tL3CHDX,
      tL3CLDX,
      04
      0b001
      + 50
      0b010
      + 100
      0b011
      + 150
      0b100
      + 200
      0b101
      + 250
      0b111
      + 300
      0b111
      + 350
      Notes:
      1. See the MPC7450 RISC Microprocessor Family User’s Manual for specific information regarding L3OHCR.
      2. See Table 13 and Table 14 for more information.
      3. Approximate delay verified by simulation; not tested or characterized
      4. Default value
      5. Increasing values of L3CLKn_OH delay the L3_CLKn signal, effectively decreasing the output valid and output hold
      times of all signals latched relative to that clock signal by the SRAM; see Figure 9 and Figure 11.
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