參數資料
型號： MC68MH360CZQ25L
廠商： Freescale Semiconductor
文件頁數： 10/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標準包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應商設備封裝： 357-PBGA（25x25）
包裝： 托盤
Chapter 6. QMC Initialization
6.3 Restarting the Transmitter
A global underrun may require the SCC transmitter to be restarted. However, for channel-
specic errors, only the affected channel need be restarted. The following steps are required
to restart each channel:
Prepare buffer descriptors.
Set the POL bit in the channel mode register.
A stopped, but not deactivated channel is started as described above. A deactivated channel
must rst have the ZISTATE and TSTATE reinitialized to their correct values, followed by
setting TSATTx[V] and CHAMR[ENT]. Lastly, set CHAMR[POL] if the buffers are ready.
6.4 Restarting the Receiver
A global receiver overrun may require the SCC receiver to be restarted. However, for
channel-specic errors, only the affected channel need be restarted. The following steps are
required to restart each channel:
Prepare buffer descriptors.
Initialize the ZDSTATE to either 0x080 (HDLC) or 0x1800_0080 (transparent).
Initialize the RSTATE to 0x3900_0000 for MH360 and 860MH.
6.5 Disabling Receiver and Transmitter
A transmit channel can be stopped from sending any more data to the line with the STOP
command described in Section 3.1, “Transmit Commands.” The transmitter will continue
to send IDLEs or FLAGs according to the channel mode register setting. To deactivate a
channel, the V bit has to be cleared in the time slot assignment table and the ENT bit has to
be cleared in the channel mode register.
To stop a channel while receiving, use the STOP command as described in Section 3.2,
“Receive Commands,” then perform a restart as described above.
6.6 Debugging Hints
Note that the following guidelines are subject to change; code should not rely on this
information. The hints are for debugging purposes only.
6.6.1 Pointer Registers
Table 6-7 discusses the debugging hints for pointer registers. See Section 2.4.1, “Channel-
Specic HDLC Parameters,” and See Section 2.4.2, “Channel-Specic Transparent
Parameters,” for more information.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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