參數(shù)資料
型號(hào): MC68MH360CZP25L
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PBGA357
封裝: 25 X 25 MM, 1.27 MM PITCH, PLASTIC, BGA-357
文件頁(yè)數(shù): 548/974頁(yè)
文件大?。?/td> 2904K
代理商: MC68MH360CZP25L
Serial Management Controllers (SMCs)
7-268
MC68360 USER’S MANUAL
MOTOROLA
7.11 SERIAL MANAGEMENT CONTROLLERS (SMCS)
The SMC key features are as follows:
Each SMC can implement the UART protocol on its own pins.
Each SMC can implement a totally transparent protocol on a multiplexed line or on a
nonmultiplexed line. This mode can also be used for a fast connection between
QUICCs.
Each SMC channel fully supports the C/I and Monitor channels of the GCI (IOM-2) in
ISDN applications.
Two SMCs fully support the two sets of C/I and Monitor channels in the SCIT channel
0 and channel. 1
Full-Duplex operation.
Local Loopback and Echo Capability for testing.
7.11.1 SMC Overview
The SMCs are two full-duplex ports that may be independently configured to support any
one of three protocols: UART, transparent, or GCI.
The SMCs can support simple UART operation for such purposes as providing a debug/
monitor port in an application, allowing the four SCCs to be free for another purpose. The
UART functionality of the SMCs is reduced as compared to the SCCs. The SMC clock can
be derived from one of the four internal baud rate generators or from an external clock pin.
The clock provided to the SMC should be a 16x clock.
The SMCs can also support totally transparent operation. In this mode, the SMC may be
connected to a TDM channel (such as a T1 line) or directly to its own set of pins. The receive
and transmit clocks can be derived from the TDM channel, the internal baud rate generators,
or from an external clock. In either case, the clock provided to the SMCs should be a 1x
clock. The transparent protocol also allows the use of an external synchronization pin for the
transmitter and receiver. The transparent functionality of the SMCs is reduced as compared
to the SCCs.
Finally, each SMC can support the C/I and monitor channels of the GCI bus (IOM-2). In this
case, the SMC is connected to a TDM channel in the SI. See 7.8 Serial Interface with Time
Slot Assigner for the details of configuring the GCI interfaces.
The SMCs support loopback and echo modes for testing.
NOTE
In the MC68302, the SMCs also provide support for the A and M
bits of the IDL definition. Since the IDL definition has been mod-
ified to eliminate the A and M bits, the QUICC does not provide
special SMC support for IDL; however, the A and M bits may still
be routed to the SMC using the TSA, if desired. The SMC would
be configured into transparent mode for this operation.
相關(guān)PDF資料
PDF描述
MC68MH360CEM25L 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP240
MC68360EM25VL 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP240
MC68MH360EM25VL 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP240
MC68360CZP25L 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PBGA357
MCE360CZP25LR2 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PBGA357
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