
Bus Operation
4-52
MC68360 USER’S MANUAL
MOTOROLA
Figure 4-36. Bus Arbitration Timing Diagram—Active Bus Case
4.6.1 Bus Request
External devices capable of becoming bus masters request the bus by asserting BR. This
signal can be wire-ORed to indicate to the QUICC that some external device requires control
of the bus. The QUICC is effectively at a lower bus priority level than the external device and
relinquishes the bus after it has completed the current bus cycle (if one has started). If no
BGACK is received while the BR is active, the QUICC remains bus master once BR is
negated. This prevents unnecessary interference with ordinary processing if the arbitration
circuitry inadvertently responds to noise or if an external device determines that it no longer
requires use of the bus before it has been granted mastership.
A31–A0
AS
DS
DSACK1–DSACK0
BR (IN)
BG (OUT)
BGACK (IN)
D31–D0
BR has synchronous timing.
S0
S2
S3
S4
S1
S5
R/W
NOTE:
CLKO1