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參數(shù)資料
| 型號(hào)： | MC68LC302PU16VCT |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁(yè)數(shù)： | 67/128頁(yè) |
| 文件大?。?/td> | 641K |
| 代理商： | MC68LC302PU16VCT |
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ETHERNET Controller
4-4
MC68EN302 REFERENCE MANUAL
MOTOROLA
This read only field is the buffer descriptor number that was being accessed when a bus
error occurred. See 4.1.5 Interrupt Event Register (INTR_EVENT) for a description of the
bus error handling.
Bit 8—Reserved. Should be written to zero by the host processor. This bit is always read as
zero.
BDSIZE1-0—Buffer descriptor size. (R/W)
00 = 8 transmit buffer descriptors, 120 receive buffer descriptors
01 = 16 transmit buffer descriptors, 112 receive buffer descriptors
10 = 32 transmit buffer descriptors, 96 receive buffer descriptors
11 = 64 transmit buffer descriptors, 64 receive buffer descriptors
BDSIZE controls the allocation of the44 128 on-chip buffer descriptors between the
transmit and receive operations. Typical implementations will set BDSIZE(1–0) to 01
allowing 16 transmit buffer descriptors and 112 receive descriptors.
TSRLY—Transmit start early. (R/W)
TSRLY controls when the transmission of a frame will begin. Typical applications will set
TSRLY to 0.
0 = Frames do not begin transmitting until the transmit FIFO has only WMRK bytes
available (empty), where WMRK ranges from 96 to 120 bytes.
1 = The frame will begin transmitting after the WMRK number of bytes have been
written to the transmit FIFO where WMRK ranges from 8 to 32 bytes. This requires
low bus latency to avoid transmit FIFO underrun.
WMRK1–0—FIFO Watermark. (R/W)
00 = 8 FIFO bytes present or available
01 = 16 FIFO bytes present or available
10 = 24 FIFO bytes present or available
11 = 32 FIFO bytes present or available
The FIFO Watermark is used to control the start of a DMA burst. In the receive direction, the
DMA state machine waits for either an end-of-frame (EOF) or a WMRK number of bytes to
be in the receive FIFO prior to beginning a DMA burst of data out of the MC68EN302 to the
host bus. In the transmit direction, the DMA state machine waits for WMRK number of bytes
TSRLY
WMRK<1:0>
BYTES IN TRANSMIT FIFO AT
START OF TRANSMISSION
0
00
120
001
112
0
10
104
011
96
100
8
101
16
110
24
111
32
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| MC68302CPV16VC | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| MC68LC302PU20VCT | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68LC302PU20CT | 功能描述:微處理器 - MPU 20MHz 2MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68LC302PU20VCT | 功能描述:IC MPU NETWORK 20MHZ 100-LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤(pán) |
| MC68LC302PU25CT | 功能描述:微處理器 - MPU 25MHz 2.5MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68LK332ACAG16 | 功能描述:32位微控制器 - MCU 32BIT MCU 2KRAM TPU QSM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MC68LK332ACAG16 | 制造商:Freescale Semiconductor 功能描述:Microcontroller |
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