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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MC68HRC908JK3CP |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 8/212闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC MCU FLASH 8B 8MHZ RC 4K 20DIP |
| 妯欐簴鍖呰锛� | 18 |
| 绯诲垪锛� | HC08 |
| 鏍稿績铏曠悊鍣細 | HC08 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 8MHz |
| 澶栧湇瑷�(sh猫)鍌欙細 | LED锛孡VD锛孭OR锛孭WM |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 15 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 4KB锛�4K x 8锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 3.3 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 12x8b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 20-DIP锛�0.300"锛�7.62mm锛� |
| 鍖呰锛� | 绠′欢 |
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Monitor ROM (MON)
MC68H(R)C908JL3 鈥� Rev. 1.1
Technical Data
Freescale Semiconductor
Monitor ROM (MON)
103
Figure 9-1. Monitor Mode Circuit
+
10
M
MC145407
MC74HC125
HC908JL3
RST
IRQ1
OSC1
OSC2
VSS
PTB0
V
DD
10 k
10k
6
5
2
4
3
1
DB-25
2
3
7
20
18
17
19
16
15
V
DD
V
DD
20 pF
10
F
10
F
10
F
10
F
1
2
4
7
14
3
0.1
F
9.8304MHz
5
6
PTB1
VDD
0.1
F
VDD
PTB2
V
DD
10 k
PTB3
V
DD
10 k
10 k
10 k
SW1
A
B
(SEE NOTE 1)
V
DD + V
HI
SW2
C
D
(SEE NOTE 4 AND 5)
NOTES:
1. X-tal circuit replaced by RC circuit for MC68HRC908xxx
2. External oscillator must have a 50% duty cycle.
3. Affects high voltage entry to monitor mode only (SW2 at position C):
SW1: Position A 鈥� Bus clock = OSC1 梅 4
SW1: Position B 鈥� Bus clock = OSC1 梅 2
4. SW2: Position C 鈥� High voltage entry to monitor mode.
Input clock = OSC1; Bus clock depends on SW1.
SW2: Position D 鈥� Bus clock source = X-TAL or RC oscillator.
Bus clock = XTALCLK 梅 4 or RCCLK 梅 4.
5. See Table 18-4 for IRQ1 voltage level requirements.
10k
V
DD
V
DD
(SEE NOTE 2)
(SEE NOTE 3)
C
D
C
D
VDD
OSC1
OSC2
RC CIRCUIT
(FOR MC68HRC908xxx)
X-TAL CIRCUIT
See Figure 18-1 for component
values vs. frequency.
HC908JK3
HC908JK1
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| MC68HRC908JL3CP | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪: 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪: |
| MC68HRC98JK1ECDW | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 8 Bit 8MHz RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| MC68HRC98JK3ECDW | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 8 Bit 8MHz RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
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