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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MC68HRC908JK3CP |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 114/212闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU FLASH 8B 8MHZ RC 4K 20DIP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 18 |
| 绯诲垪锛� | HC08 |
| 鏍稿績铏曠悊鍣細 | HC08 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 8MHz |
| 澶栧湇瑷�(sh猫)鍌欙細 | LED锛孡VD锛孭OR锛孭WM |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 15 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 4KB锛�4K x 8锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 3.3 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 12x8b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 20-DIP锛�0.300"锛�7.62mm锛� |
| 鍖呰锛� | 绠′欢 |
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Electrical Specifications
Technical Data
MC68H(R)C908JL3 鈥� Rev. 1.1
198
Electrical Specifications
Freescale Semiconductor
18.10 3V Control Timing
NOTES:
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25
掳C only.
3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 4MHz); all inputs 0.2 V from rail; no dc loads;
less than 100 pF on all outputs. CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly af-
fects wait IDD.
5. STOP IDD measured with OSC1 grounded, no port pins sourcing current. LVI is disabled.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until
minimum VDD is reached.
8. RPU1 and RPU2 are measured at VDD = 5.0V
Table 18-8. Control Timing (3V)
Characteristic(1)
NOTES:
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise
noted.
Symbol
Min
Max
Unit
Internal operating frequency(2)
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor-
mation.
fOP
鈥�4
MHz
RST input pulse width low(3)
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
tIRL
1.5
鈥�
s
Table 18-7. DC Electrical Characteristics (3V)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MC68HRC908JL3CP | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪: 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪: |
| MC68HRC98JK1ECDW | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 8 Bit 8MHz RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| MC68HRC98JK3ECDW | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 8 Bit 8MHz RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| MC68HRC98JL3ECDW | 鍔熻兘鎻忚堪:IC MCU 4K FLASH 8MHZ 28-SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:HC08 妯�(bi膩o)婧�(zh菙n)鍖呰:250 绯诲垪:56F8xxx 鏍稿績铏曠悊鍣�:56800E 鑺珨灏哄:16-浣� 閫熷害:60MHz 閫ｉ€氭€�:CAN锛孲CI锛孲PI 澶栧湇瑷�(sh猫)鍌�:POR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):21 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲�:40KB锛�20K x 16锛� 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:6K x 16 闆诲 - 闆绘簮 (Vcc/Vdd):2.25 V ~ 3.6 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 6x12b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:48-LQFP 鍖呰:鎵樼洡 閰嶇敤:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| MC68HSC705C8ACFB | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:8 BIT MCU, 304 BYTES RAM - Bulk |
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