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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� MC68HRC908JK3CDW
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 181/212闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 4K FLASH 8MHZ SO20
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 38
绯诲垪锛� HC08
鏍稿績铏曠悊鍣細 HC08
鑺珨灏哄锛� 8-浣�
閫熷害锛� 8MHz
澶栧湇瑷�(sh猫)鍌欙細 LED锛孡VD锛孭OR锛孭WM
杓稿叆/杓稿嚭鏁�(sh霉)锛� 15
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 4KB锛�4K x 8锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 128 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 3.3 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 12x8b
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 20-SOIC锛�0.295"锛�7.50mm 瀵級
鍖呰锛� 绠′欢
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Central Processor Unit (CPU)
Technical Data
MC68H(R)C908JL3 鈥� Rev. 1.1
68
Central Processor Unit (CPU)
Freescale Semiconductor
A
Accumulator
n
Any bit
C
Carry/borrow bit
opr
Operand (one or two bytes)
CCR
Condition code register
PC
Program counter
dd
Direct address of operand
PCH Program counter high byte
dd rr
Direct address of operand and relative offset of branch instruction
PCL Program counter low byte
DD
Direct to direct addressing mode
REL Relative addressing mode
DIR
Direct addressing mode
rel
Relative program counter offset byte
DIX+
Direct to indexed with post increment addressing mode
rr
Relative program counter offset byte
ee ff
High and low bytes of offset in indexed, 16-bit offset addressing
SP1 Stack pointer, 8-bit offset addressing mode
EXT
Extended addressing mode
SP2 Stack pointer 16-bit offset addressing mode
ff
Offset byte in indexed, 8-bit offset addressing
SP
Stack pointer
H
Half-carry bit
U
Undefined
H
Index register high byte
V
Overflow bit
hh ll
High and low bytes of operand address in extended addressing
X
Index register low byte
I
Interrupt mask
Z
Zero bit
ii
Immediate operand byte
&
Logical AND
IMD
Immediate source to direct destination addressing mode
|
Logical OR
IMM
Immediate addressing mode
鈯�
Logical EXCLUSIVE OR
INH
Inherent addressing mode
( )
Contents of
IX
Indexed, no offset addressing mode
鈥�( )
Negation (two鈥檚 complement)
IX+
Indexed, no offset, post increment addressing mode
#
Immediate value
IX+D
Indexed with post increment to direct addressing mode
Sign extend
IX1
Indexed, 8-bit offset addressing mode
鈫�
Loaded with
IX1+
Indexed, 8-bit offset, post increment addressing mode
?
If
IX2
Indexed, 16-bit offset addressing mode
:
Concatenated with
M
Memory location
Set or cleared
N
Negative bit
鈥�
Not affected
Table 6-1. Instruction Set Summary
Source
Form
Operation
Description
Effect on
CCR
Ad
dress
Mode
Op
cod
e
Operan
d
Cyc
les
VH I N Z C
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