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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MC68HC908QT2CP |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 15/184闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU 1.5K FLASH W/ADC 8-DIP |
| 妯�(bi膩o)婧栧寘瑁濓細 | 50 |
| 绯诲垪锛� | HC08 |
| 鏍稿績铏曠悊鍣細 | HC08 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 8MHz |
| 澶栧湇瑷�(sh猫)鍌欙細 | LVD锛孭OR锛孭WM |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 5 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 1.5KB锛�1.5K x 8锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 4x8b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 8-DIP锛�0.300"锛�7.62mm锛� |
| 鍖呰锛� | 绠′欢 |
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Exception Control
MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor
111
Figure 13-8
. Interrupt Entry
Figure 13-9. Interrupt Recovery
13.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 13-10 demonstrates what happens when two interrupts are pending. If an interrupt
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
The LDA opcode is prefetched by both the INT1 and INT2 return-from-interrupt (RTI) instructions.
However, in the case of the INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
MODULE
DATA BUS
R/W
INTERRUPT
DUMMY
SP
SP 鈥� 1
SP 鈥� 2
SP 鈥� 3
SP 鈥� 4
VECT H
VECT L
START ADDR
ADDRESS BUS
DUMMY
PC 鈥� 1[7:0] PC 鈥� 1[15:8]
X
A
CCR
V DATA H
V DATA L
OPCODE
I BIT
MODULE
DATA BUS
R/W
INTERRUPT
SP 鈥� 4
SP 鈥� 3
SP 鈥� 2
SP 鈥� 1
SP
PC
PC + 1
ADDRESS BUS
CCR
A
X
PC 鈥� 1[7:0] PC 鈥� 1[15:8] OPCODE
OPERAND
I BIT
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MC68HC908QT1CDW | IC MCU 1.5K FLASH 8-SOIC |
| EHFW2B | CONN EEE1394 FEMALE STR T/H BLK |
| MC68HC908QT1CP | IC MCU 1.5K FLASH 8-DIP |
| C8051F585-IQ | IC 8051 MCU 96K FLASH 48-QFP |
| C8051F586-IM | IC 8051 MCU 96K FLASH 32-QFN |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MC68HC908QT2CPE | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 1.5K FLASH W/ADC RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| MC68HC908QT2MDW | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:1.5K FLASH W/ADC - Bulk |
| MC68HC908QT2MP | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk 鍒堕€犲晢:Motorola Inc 鍔熻兘鎻忚堪: 鍒堕€犲晢:MOTOROLA 鍔熻兘鎻忚堪: |
| MC68HC908QT2MPE | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 1.5K FLASH W/ADC RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| MC68HC908QT2VDW | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪: |
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