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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� MC68HC908JK3CDW
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 37/212闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MCU 8MHZ 4K FLASH 20-SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 38
绯诲垪锛� HC08
鏍稿績铏曠悊鍣細 HC08
鑺珨灏哄锛� 8-浣�
閫熷害锛� 8MHz
澶栧湇瑷�(sh猫)鍌欙細 LED锛孡VD锛孭OR锛孭WM
杓稿叆/杓稿嚭鏁�(sh霉)锛� 15
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 4KB锛�4K x 8锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 128 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 3.3 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 12x8b
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 20-SOIC锛�0.295"锛�7.50mm 瀵級
鍖呰锛� 绠′欢
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Timer Interface Module (TIM)
MC68H(R)C908JL3 鈥� Rev. 1.1
Technical Data
Freescale Semiconductor
Timer Interface Module (TIM)
129
10.10.2 TIM Counter Registers (TCNTH:TCNTL)
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE:
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Table 10-2. Prescaler Selection
PS2
PS1
PS0
TIM Clock Source
0
Internal Bus Clock 梅 1
0
1
Internal Bus Clock 梅 2
0
1
0
Internal Bus Clock 梅 4
0
1
Internal Bus Clock 梅 8
1
0
Internal Bus Clock 梅 16
1
0
1
Internal Bus Clock 梅 32
1
0
Internal Bus Clock 梅 64
1
Not available
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
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MC68HC908JK8MDWE 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪: