Timing System
Data Sheet
M68HC11E Family — Rev. 5
158
Timing System
MOTOROLA
9.5.2 Timer Interrupt Flag Register 2
Bits of this register indicate the occurrence of timer system events. Coupled with
the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to
operate in either a polled or interrupt driven system. Each bit of TFLG2
corresponds to a bit in TMSK2 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time Interrupt Flag
The RTIF status bit is automatically set to 1 at the end of every RTI period. To
clear RTIF, write a byte to TFLG2 with bit 6 set.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
Refer to
9.7 Pulse Accumulator
.
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Refer to
9.7 Pulse Accumulator
.
Bits [3:0] — Unimplemented
Always read 0
Address:
$1025
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TOF
RTIF
PAOVF
PAIF
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-22. Timer Interrupt Flag 2 Register (TFLG2)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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