Parallel Input/Output (I/O) Ports
Data Sheet
M68HC11E Family — Rev. 5
110
Parallel Input/Output (I/O) Ports
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MOTOROLA
DDRA7 — Data Direction for Port A Bit 7
Overridden if an output compare function is configured to control the PA7 pin
0 = Input
1 = Output
The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also
be used as general-purpose I/O or as an output compare.
NOTE:
Even when port A bit 7 is configured as an output, the pin still drives the input to
the pulse accumulator.
PAEN — Pulse Accumulator System Enable Bit
Refer to
Section 9. Timing System
.
PAMOD — Pulse Accumulator Mode Bit
Refer to
Section 9. Timing System
.
PEDGE — Pulse Accumulator Edge Control Bit
Refer to
Section 9. Timing System
.
DDRA3 — Data Direction for Port A Bit 3
This bit is overridden if an output compare function is configured to control the
PA3 pin.
0 = Input
1 = Output
I4/O5 — Input Capture 4/Output Compare 5 Bit
Refer to
Section 9. Timing System
.
RTR[1:0] — RTI Interrupt Rate Select Bits
Refer to
Section 9. Timing System
.
Address:
$1000
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Write:
Reset:
I
0
0
0
I
I
I
I
Alternate function:
PAI
OC2
OC3
OC4
IC4/OC5
IC1
IC2
IC3
And/or:
OC1
OC1
OC1
OC1
OC1
—
—
—
I = Indeterminate after reset
Figure 6-1. Port A Data Register (PORTA)
Address:
$1026
Bit 7
6
5
4
3
2
1
Bit 0
Read:
DDRA7
PAEWN
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 6-2. Pulse Accumulator Control Register (PACTL)
F
Freescale Semiconductor, Inc.
n
.
