參數(shù)資料
型號： MC68HC705SR3CPE
廠商： Freescale Semiconductor
文件頁數(shù)： 36/96頁
文件大?。?/td> 0K
描述： IC MCU 3.75K 2.1MHZ OTP 40-DIP
標準包裝： 9
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 4MHz
外圍設備： LED，POR
輸入/輸出數(shù)： 32
程序存儲器容量： 3.75KB（3.75K x 8）
程序存儲器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 4x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
MC68HC05SR3
Freescale
5-5
RESETS AND INTERRUPTS
5
5.2.2
Maskable Hardware Interrupts
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts are masked. Clearing the
I-bit allows interrupt processing to occur.
Note:
The internal interrupt latch is cleared in the first part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the
I-bit is cleared.
5.2.2.1
External Interrupt (IRQ)
The external interrupt IRQ is controlled by two bits in the Miscellaneous Control Register ($0C).
INTE — INTerrupt Enable
1 (set)
–
External interrupt IRQ is enabled.
0 (clear) –
External interrupt is disabled.
The external IRQ is default enabled at power-on reset.
INTO — INTerrupt Option
1 (set)
–
Negative-edge sensitive triggering for IRQ.
0 (clear) –
Negative-level sensitive triggering for IRQ.
When the signal of the external interrupt pin, IRQ, satisfies the condition selected, an external
interrupt occurs. The actual processor interrupt is generated only if the interrupt mask bit of the
condition code register is also cleared. When the interrupt is recognized, the current state of the
processor is pushed onto the stack and the interrupt mask bit in the Condition Code Register is
set. This masks further interrupts until the present one is serviced. The service routine address is
specified by the contents in $1FFA-$1FFB.
The interrupt logic recognizes negative edge transitions and pulses (special case of negative
edges) on the external interrupt line. Figure 5-3 shows both a block diagram and timing for the
interrupt line (IRQ) to the processor. The first method is used if pulses on the interrupt line are
spaced far enough apart to be serviced. The minimum time between pulses is equal to the number
of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the
next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The
second configuration shows several interrupt lines wired-OR to perform the interrupt at the
processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is
recognized.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Miscellaneous Control Register
$0C
KBIE
KBIC
INTO
INTE LVRE
SM
IRQ2F IRQ2E 0001 0000
TPG
39
05SR3.Book Page 5 Thursday, August 4, 2005 1:08 PM
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相關代理商/技術參數(shù)
參數(shù)描述
MC68HC705SR3CPE 制造商:Freescale Semiconductor 功能描述:8-Bit Microcontroller IC
MC68HC705SR3PE 功能描述:IC MCU 3.75K 2.1MHZ OTP 40-DIP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 標準包裝:1 系列:AVR® ATmega 核心處理器:AVR 芯體尺寸:8-位 速度:16MHz 連通性:I²C，SPI，UART/USART 外圍設備:欠壓檢測/復位，POR，PWM，WDT 輸入/輸出數(shù):32 程序存儲器容量:32KB（16K x 16） 程序存儲器類型:閃存 EEPROM 大小:1K x 8 RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:44-TQFP 包裝:剪切帶 (CT) 其它名稱:ATMEGA324P-B15AZCT
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