When the LVR function is enabled, an internal reset i" />
參數(shù)資料
型號(hào)： MC68HC705SR3CPE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 32/96頁(yè)
文件大?。?/td> 0K
描述： IC MCU 3.75K 2.1MHZ OTP 40-DIP
標(biāo)準(zhǔn)包裝： 9
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 4MHz
外圍設(shè)備： LED，POR
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 3.75KB（3.75K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
Freescale
5-2
MC68HC05SR3
RESETS AND INTERRUPTS
5
5.1.3
Low Voltage Reset (LVR)
When the LVR function is enabled, an internal reset is generated if the supply voltage, VDD, drops
below VLVR. (See Section 11 for value of VLVR).
This LVR function is enabled by setting the LVRE bit in the Miscellaneous Control Register.
LVRE — Low Voltage Reset Enable
1 (set)
–
Low Voltage Reset function enabled.
0 (clear) –
Low Voltage Reset function disabled.
Note:
The LVR function should not be enabled when operating VDD=3V.
5.2
INTERRUPTS
The MC68HC05SR3 MCU can be interrupted by different sources – four maskable hardware
interrupt and one non-maskable software interrupt:
Software Interrupt Instruction (SWI)
External signal on IRQ pin
External signal on IRQ2 pin
TImer Overflow
Keyboard
If the interrupt mask bit (I-bit) in the Condition Code Register (CCR) is set, all maskable interrupts
are disabled. Clearing the I-bit enables interrupts.
Interrupts cause the processor to save the register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. The RTI instruction causes the register contents to be
recovered from the stack and normal processing to resume.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete. The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) the
processor proceeds with interrupt processing; otherwise, the next instruction is fetched and
executed. Table 5-1 shows the relative priority of all the possible interrupt sources. Figure 5-2
shows the interrupt processing flow.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Miscellaneous Control Register
$0C
KBIE
KBIC
INTO
INTE LVRE
SM
IRQ2F IRQ2E 0001 0000
TPG
36
05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM
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參數(shù)描述
MC68HC705SR3CPE 制造商:Freescale Semiconductor 功能描述:8-Bit Microcontroller IC
MC68HC705SR3PE 功能描述:IC MCU 3.75K 2.1MHZ OTP 40-DIP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 標(biāo)準(zhǔn)包裝:1 系列:AVR® ATmega 核心處理器:AVR 芯體尺寸:8-位 速度:16MHz 連通性:I²C，SPI，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，POR，PWM，WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:32KB（16K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:1K x 8 RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:44-TQFP 包裝:剪切帶 (CT) 其它名稱:ATMEGA324P-B15AZCT
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