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| 型號(hào)： | MC68HC705JB4P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 87/134頁(yè) |
| 文件大?。?/td> | 1305K |
| 代理商： | MC68HC705JB4P |
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GENERAL RELEASE SPECIFICATION
February 24, 1999
MOTOROLA
MULTI-FUNCTION TIMER
MC68HC05JB4
8-4
REV 2
RTIF - Real Time Interrupt Flag
The RTIF is a read-only ag bit.
1 =
Set when the output of the chosen (1 of 4 selections) Real Time
Interrupt stage goes active. A TIMER Interrupt request will be
generated if RTIE is also set.
0 =
Reset by writing a logical one to the RTIF acknowledge bit, RTIFR.
Writing to the RTIF ag bit has no effect on its value. This bit is
cleared by reset.
TOFE - Timer Overow Enable
The TOFE is an enable bit that allows generation of a TIMER Interrupt upon
overow of the Timer Counter Register.
1 =
When set, the TIMER Interrupt is generated when the TOF ag bit is
set.
0 =
When cleared, no TIMER interrupt caused by TOF bit set will be
generated. This bit is cleared by reset.
RTIE - Real Time Interrupt Enable
The RTIE is an enable bit that allows generation of a TIMER Interrupt by the
RTIF bit.
1 =
When set, the TIMER Interrupt is generated when the RTIF ag bit is
set.
0 =
When cleared, no TIMER interrupt caused by RTIF bit set will be
generated. This bit is cleared by reset.
TOFR - Timer Overow Acknowledge
The TOFR is an acknowledge bit that resets the TOF ag bit. This bit is unaf-
fected by reset. Reading the TOFR will always return a logical zero.
1 =
Clears the TOF ag bit.
0 =
Does not clear the TOF ag bit.
RTIFR - Real Time Interrupt Acknowledge
The RTIFR is an acknowledge bit that resets the RTIF ag bit. This bit is unaf-
fected by reset. Reading the RTIFR will always return a logical zero.
1 =
Clears the RTIF ag bit.
0 =
Does not clear the RTIF ag bit.
8.4
OPERATION DURING STOP MODE
When STOP is exited by an external interrupt or an LVR reset or an external
RESET, the internal oscillator will resume, followed by a 128 or 4064 internal pro-
cessor oscillator stabilization delay.
8.5
COP CONSIDERATION DURING STOP MODE
In STOP mode, the clock to the Watchdog Timer is stopped and is therefore
impossible to generate COP reset when in STOP mode. The COP function will
resume 128 or 4064 cycles after exiting from STOP.
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