參數(shù)資料
型號(hào): MC68HC705J1ACDW
廠商: Freescale Semiconductor
文件頁數(shù): 32/162頁
文件大小: 0K
描述: IC MCU 4MHZ 1.2K OTP 20-SOIC
標(biāo)準(zhǔn)包裝: 38
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 14
程序存儲(chǔ)器容量: 1.2KB(1.2K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 管件
Electrical Specifications
3.3-Volt Control Timing
MC68HC705J1A — Rev. 4.0
Technical Data
Electrical Specifications
10.13 3.3-Volt Control Timing
Characteristic(1)
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted
Symbol
Min
Max
Unit
Oscillator frequency
Crystal oscillator option
External clock source
fosc
dc
2.0
MHz
Internal operating frequency (fosc ÷ 2)
Crystal oscillator
External clock
fop
dc
1.0
MHz
Cycle time (1
÷ f
OP)t
cyc
1000
ns
RESET pulse width low
tRL
1.5
tcyc
IRQ interrupt pulse width low (edge-triggered)
tILIH
1.5
tcyc
IRQ interrupt pulse width low (edge- and level-triggered)
tILIL
1.5
Note(2)
2. The maximum width, tILIL or tILIH, should not be more than the number of cycles it takes to execute the interrupt service
routine plus 19 tcyc or the interrupt service routine will be re-entered.
tcyc
PA0–PA3 interrupt pulse width high (edge-triggered)
tIHIL
1.5
tcyc
PA0–PA3 interrupt pulse width (edge- and level-triggered)
tIHIH
1.5
Note(2)
tcyc
OSC1 pulse width
tOH, tOL
400
ns
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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