參數(shù)資料
型號: MC68HC705J1ACDW
廠商: Freescale Semiconductor
文件頁數(shù): 18/162頁
文件大?。?/td> 0K
描述: IC MCU 4MHZ 1.2K OTP 20-SOIC
標(biāo)準(zhǔn)包裝: 38
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 14
程序存儲器容量: 1.2KB(1.2K x 8)
程序存儲器類型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 管件
Technical Data
MC68HC705J1A — Rev. 4.0
Multifunction Timer Module
Multifunction Timer Module
interrupt request to be generated. To prevent this occurrence, clear the
COP timer before changing RT1 and RT0.
9.5.2 Timer Counter Register
A 15-stage ripple counter is the core of the timer. The value of the first
eight stages is readable at any time from the read-only timer counter
register (TCR) shown in Figure 9-4.
Power-on clears the entire counter chain and the internal clock begins
clocking the counter. After 4064 cycles (or 16 cycles if the SOSCD bit in
the mask option register is set), the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer
interrupt every 1024 internal clock cycles.
Table 9-1. Real-Time Interrupt Rate Selection
RT1:RT0
Number
of Cycles
to RTI
RTI
Period(1)
1. At 2-MHz bus, 4-MHz XTAL, 0.5
s per cycle
Number
of Cycles
to COP Reset
COP Timeout
Period(1)
0 0
214 = 16,384
8.2 ms
217 = 131,072
65.5 ms
0 1
215 = 32,768
16.4 ms
218 = 262,144
131.1 ms
1 0
216 = 65,536
32.8 ms
219 = 524,288
262.1 ms
1 1
217 = 131,072
65.5 ms
220 = 1,048,576
524.3 ms
Address:
$0009
Bit 7
6
54321
Bit 0
Read:
TMR7
TMR6
TMR5
TMR4
TMR3
TMR2
TMR1
TMR0
Write:
Reset:
00
000000
= Unimplemented
Figure 9-4. Timer Counter Register (TCR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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