List of Figures
Advance Information
MC68HC705C9A — Rev. 4.0
16
List of Figures
MOTOROLA
Figure
Title
Page
7-1
7-2
Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Port B I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
8-1
8-2
8-3
8-4
8-5
8-6
8-7
Capture/Compare Timer Block Diagram. . . . . . . . . . . . . . . . . .74
Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . .76
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . .78
Timer Registers (TRH and TRL). . . . . . . . . . . . . . . . . . . . . . . .79
Alternate Timer Registers (ATRH and ATRL). . . . . . . . . . . . . .80
Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . . . . .81
Output Compare Registers (OCRH and OCRL). . . . . . . . . . . .82
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
Serial Communications Interface Block Diagram . . . . . . . . . . .87
Rate Generator Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
SCI Examples of Start Bit Sampling Techniques . . . . . . . . . . .92
SCI Sampling Technique Used on All Bits . . . . . . . . . . . . . . . .92
SCI Artificial Start Following a Frame Error . . . . . . . . . . . . . . .93
SCI Start Bit Following a Break . . . . . . . . . . . . . . . . . . . . . . . .94
SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . . . .94
SCI Control Register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . . . .95
SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . . . .96
SCI Status Register (SCSR). . . . . . . . . . . . . . . . . . . . . . . . . . .99
Baud Rate Register (BAUD). . . . . . . . . . . . . . . . . . . . . . . . . .101
10-1
10-2
10-3
10-4
10-5
10-6
Data Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .105
Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . .107
Serial Peripheral Interface Master-Slave Interconnection . . .108
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . .109
SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
PI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
12-1
12-2
Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Maximum Supply Current vs Internal
Clock Frequency, V
DD
= 5.5 V. . . . . . . . . . . . . . . . . . . . . .137
Maximum Supply Current vs Internal
Clock Frequency, V
DD
= 3.6 V. . . . . . . . . . . . . . . . . . . . . .137
12-3
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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