參數(shù)資料
型號(hào): MC68HC705C9ACP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Microcontrollers
中文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝: PLASTIC, DIP-40
文件頁數(shù): 141/160頁
文件大小: 2076K
代理商: MC68HC705C9ACP
Electrical Specifications
3.3-Vdc Control Timing
MC68HC705C9A — Rev. 4.0
Advance Information
MOTOROLA
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
141
Figure 12-7. Power-On Reset Timing Diagram
Figure 12-8. External Reset Timing
3FFE
4064 t
CYC
V
DD
OSC1 PIN
(2)
INTERNAL
CLOCK
(3)
INTERNAL
DATA BUS
(3)
3FFE
3FFE
3FFE
3FFE
3FFE
3FFF
(NOTE 1)
1. Power-on reset threshold is typically between 1 V and 2 V.
2. OSC1 line is meant to represent time only, not frequency.
3. Internal clock, internal address bus, and internal data bus are not available externally.
4. RESET outputs V
OL
during 4064 POR cycles.
NEW
PCH
NEW
PCL
Notes:
RESET PIN
(NOTE 4)
INTERNAL
ADDRESS BUS
(3)
INTERNAL
CLOCK
(1)
INTERNAL
ADDRESS BUS
(1)
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
INTERNAL
DATA BUS
(1)
3FFE
3FFE
3FFF
NEW PC
NEW
PCH
t
RL
NEW
PCL
OP
CODE
RESET
(2)
3FFE
3FFE
F
Freescale Semiconductor, Inc.
n
.
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