參數(shù)資料
型號: MC68HC705C9ACFN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Microcontrollers
中文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 142/160頁
文件大?。?/td> 2076K
代理商: MC68HC705C9ACFN
Electrical Specifications
Advance Information
MC68HC705C9A — Rev. 4.0
142
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
12.10 5.0-Vdc Serial Peripheral Interface Timing
No.
Characteristic
(1)
1. V
= 5.0 Vdc
±
10%; V
= 0 Vdc, T
= –40 to +85
°
C, unless otherwise noted. Refer to
Figure 12-9
and
Figure 12-10
.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins.
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
f
OP
(
M
)
f
OP
(
S
)
dc
dc
0.5
2.1
f
OP
MHz
1
Cycle time
Master
Slave
t
CYC
(
M
)
t
CYC
(
S
)
2.0
480
t
CYC
ns
2
Enable lead time
Master
Slave
t
LEAD
(
M
)
t
LEAD
(
S
)
(2)
240
ns
3
Enable lag time
Master
Slave
t
LAG
(
M
)
t
LAG
(
S
)
(2)
720
ns
4
Clock (SCK) high time
Master
Slave
t
W
(
SCKH
)
M
t
W
(
SCKH
)
S
340
190
ns
5
Clock (SCK) low time
Master
Slave
t
W
(
SCKL
)
M
t
W
(
SCKL
)
S
340
190
ns
6
Data setup time (inputs)
Master
Slave
t
SU
(
M
)
t
SU
(
S
)
100
100
ns
7
Data hold time (inputs)
Master
Slave
Slave access time (time to data active from
high-impedance state)
Slave disable time (hold time to high-impedance state)
Data valid
Master (before capture edge)
Slave (after enable edge)
(3)
Data hold time (outputs)
Master (after capture edge)
slave (After Enable Edge)
t
H
(
M
)
t
H
(
S
)
100
100
ns
8
t
A
0
120
ns
9
t
DIS
240
ns
10
t
V
(
M
)
t
V
(
S
)
0.25
240
t
CYC
(
M
)
ns
11
t
HO
(
M
)
t
HO
(
S
)
0.25
0
t
CYC
(
M
)
ns
12
Rise time (20% V
DD
to 70% V
DD
, C
L
= 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
Fall time (70% V
DD
to 20% V
DD
, C
L
= 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t
RM
t
RS
100
2.0
ns
μ
s
13
t
FM
t
FS
100
2.0
ns
μ
s
F
Freescale Semiconductor, Inc.
n
.
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