Technical Data
M68HC11K Family
52
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
3.3.6.7 Non-Maskable Interrupt (X)
Setting the XIRQ mask (X) bit disables non-maskable interrupts from the
XIRQ pin. Every reset sets the X bit by default and only a software
instruction can clear it. When the processor recognizes a non-maskable
interrupt, it stacks the registers, sets the X and I bits, and then fetches
the interrupt vector. An interrupt service routine usually ends with a
return from interrupt (RTI), which restores the registers to the values that
were present before the interrupt occurred and clears the X bit. Only
hardware or an acknowledge can set the X bit. Only software can clear
the X bit (for example, the TAP instruction which transfers data from
accumulator A to the condition code register). There is no hardware
action for clearing X.
3.3.6.8 Stop Disable (S)
Setting the STOP disable (S) bit prevents the STOP instruction from
putting the M68HC11 into a low-power stop condition. If the S bit is set,
the CPU treats a STOP instruction as if it were a no-operation (NOP)
instruction and continues to the next instruction.
NOTE:
S is set by reset and STOP is disabled by default.
The STOP instruction can be cleared by using the TAP instruction which
transfers data from accumulator A to the condition code register.
3.4 Data Types
The MC68HC11 CPU supports these data types:
Bit data
8-bit and 16-bit signed and unsigned integers
16-bit unsigned fractions
16-bit addresses
A byte is eight bits wide and can be accessed at any byte location. A
word is composed of two consecutive bytes with the most significant
byte at the lower value address. Because the M68HC11 is an 8-bit CPU,
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Freescale Semiconductor, Inc.
For More Information On This Product,
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