Technical Data
M68HC11K Family
50
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
3.3.5 Program Counter (PC)
The 16-bit program counter contains the address of the next instruction
to be executed. Its initial value after reset is fetched from one of six
possible vectors, depending on operating mode and the cause of reset,
3.3.6 Condition Code Register (CCR)
This 8-bit register contains:
Five condition code indicators (C, V, Z, N, and H)
Two interrupt masking bits (IRQ and XIRQ)
A stop disable bit (S)
Most instructions update condition codes automatically, as described in
the following paragraphs. Certain instructions, such as pushes, pulls,
add B to X (ABX), add B to Y (ABY), and transfer/exchange instructions
do not affect the condition codes. Table 3-1 shows which condition
codes are affected by each instruction.
3.3.6.1 Carry/Borrow (C)
The C bit is set if the CPU performs a carry or borrow during an
arithmetic operation. This bit also acts as an error flag for multiply and
divide operations. Shift and rotate instructions operate with and through
the carry bit to facilitate multiple-word shift operations.
3.3.6.2 Overflow (V)
The overflow bit is set if an operation results in a two’s complement
overflow of the 8-bit signed range –128 to +127. Otherwise, the V bit is
cleared.
3.3.6.3 Zero (Z)
The Z bit is set if the result of an arithmetic, logic, or data manipulation
operation is 0. Otherwise, the Z bit is cleared. Compare instructions do
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Freescale Semiconductor, Inc.
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