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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MC68HC11F1CFN4
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 55/158闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 512 EEPROM 4MHZ 68-PLCC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 18
绯诲垪锛� HC11
鏍稿績铏曠悊鍣細 HC11
鑺珨灏哄锛� 8-浣�
閫熷害锛� 4MHz
閫ｉ€氭€э細 SCI锛孲PI
澶栧湇瑷�(sh猫)鍌欙細 POR锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 30
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 ROMless
EEPROM 澶�?銆�?/td> 512 x 8
RAM 瀹归噺锛� 1K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4.75 V ~ 5.25 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x8b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 68-LCC锛圝 褰㈠紩绶氾級
鍖呰锛� 绠′欢
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�鐣�(d膩ng)鍓嶇55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�
ELECTRICAL CHARACTERISTICS
MC68HC11F1
A-14
TECHNICAL DATA
NOTES:
1. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins.
Table A-8 Serial Peripheral Interface Timing
VDD = 5.0 Vdc 卤 5%, VSS = 0 Vdc, TA = TL to TH
Num
Characteristic
Symbol
2.0 MHz
3.0 MHz
4.0 MHz
Unit
Min
Max
Min
Max
Min
Max
Operating Frequency
Master
Slave
fop(m)
fop(s)
dc
1.0
2.0
dc
1.5
3.0
dc
2.0
4.0
MHz
1
Cycle Time
Master
Slave
tcyc(m)
tcyc(s)
2.0
500
鈥�
2.0
333
鈥�
2.0
250
鈥�
tcyc
ns
2
Enable Lead Time
Master
(Note 2)
Slave
tlead(m)
tlead(s)
鈥�
250
鈥�
240
鈥�
200
鈥�
ns
3
Enable Lag Time
Master
(Note 2)
Slave
tlag(m)
tlag(s)
鈥�
250
鈥�
240
鈥�
200
鈥�
ns
4
Clock (SCK) High Time
Master
Slave
tw(SCKH)m
tw(SCKH)s
340
190
鈥�
227
127
鈥�
130
85
鈥�
ns
5
Clock (SCK) Low Time
Master
Slave
tw(SCKL)m
tw(SCKL)s
340
190
鈥�
227
127
鈥�
130
85
鈥�
ns
6
Data Setup Time (Inputs)
Master
Slave
tsu(m)
tsu(s)
100
鈥�
100
鈥�
100
鈥�
ns
7
Data Hold Time (Inputs)
Master
Slave
th(m)
th(s)
100
鈥�
100
鈥�
100
鈥�
ns
8
Access Time (Time to Data Active from
High-Impedance State)
Slave
ta
0
120
0
120
0
120
ns
9
Disable Time (Hold Time to High-Impedance State)
Slave
tdis
鈥�
240
鈥�
167
鈥�
125
ns
10
Data Valid (After Enable Edge)
(Note 3)
tv(s)
鈥�
240
鈥�
167
鈥�
125
ns
11
Data Hold Time (Outputs) (After Enable Edge)
tho
0鈥�0鈥�0鈥�
ns
12
Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
trm
trs
鈥�
100
2.0
鈥�
100
2.0
鈥�
100
2.0
ns
s
13
Fall Time (70% VDD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tfm
tfs
鈥�
100
2.0
鈥�
100
2.0
鈥�
100
2.0
ns
s
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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