參數(shù)資料
型號(hào): MC68HC11F1CFN2
廠商: Freescale Semiconductor
文件頁數(shù): 27/158頁
文件大?。?/td> 0K
描述: IC MCU 512 EEPROM 2MHZ 68-PLCC
標(biāo)準(zhǔn)包裝: 18
系列: HC11
核心處理器: HC11
芯體尺寸: 8-位
速度: 2MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 30
程序存儲(chǔ)器類型: ROMless
EEPROM 大?。?/td> 512 x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-LCC(J 形引線)
包裝: 管件
TIMING SYSTEM
MC68HC11F1
9-16
TECHNICAL DATA
Figure 9-3 Pulse Accumulator
Pulse accumulator control bits are also located within two timer registers, TMSK2 and
TFLG2, as described in the following paragraphs.
9.6.1 Pulse Accumulator Control Register
Four of this register's bits control an 8-bit pulse accumulator system. Another bit en-
ables either the OC5 function or the IC4 function, while two other bits select the rate
for the real-time interrupt system.
Table 9-5 Pulse Accumulator Timing
Crystal Frequency
(4
E)
E Clock
(E)
Cycle Time
(1/E)
26/E
(64/E)
PACNT Overflow
(16384/E)
4.0 MHz
1.0 MHz
1000 ns
64
s
16.384 ms
8.0 MHz
2.0 MHz
500 ns
32
s
8.192 ms
12.0 MHz
3.0 MHz
333 ns
21.33
s
5.461 ms
16.0 MHz
4.0 MHz
250 ns
16.0
s
4.096 ms
PEDGE
PAMOD
PAEN
PACTL CONTROL
INTERNAL
DATA BUS
PACNT 8-BIT COUNTER
PA7/
PAI/
OC1
INTERRUPT
REQUESTS
PAIF
PAOVF
TFLG2 INTERRUPT STATUS
PAOVI
PAII
PAOVF
PAOVI
PAIF
PAII
TMSK2 INT ENABLES
1
2
OVERFLOW
ENABLE
DISABLE
FLAG SETTING
CLOCK
PAI EDGE
PAEN
2:1
MUX
OUTPUT
BUFFER
INPUT BUFFER
AND
EDGE DETECTOR
FROM
MAIN TIMER
OC1
DATA BUS
PIN
E
÷ 64 CLOCK
(FROM MAIN TIMER)
FROM DATA
DIRECTION
BIT FOR
PORT A PIN 7
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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