參數(shù)資料
型號(hào)： MC68HC11EA9MFN2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁(yè)數(shù)： 39/58頁(yè)
文件大小： 583K
代理商： MC68HC11EA9MFN2
MOTOROLA
MC68HC11EA9
44
MC68HC11EA9TS/D
Figure 10 Pulse Accumulator Block Diagram
Bits [7:4] can be written at any time. PR[1:0] can only be written once in the first 64 cycles after reset in
normal modes (SMOD = 0). In special modes (SMOD = 1) PR[1:0] can be written any time.
Bit 7 — Not Implemented
Always reads zero
PAEN — Pulse Accumulator Enable
0 = Periodic interrupts are disabled
1 = Interrupts are generated at the rate determined by RTR[1:0]
PAMOD — Pulse Accumulator Mode Select
0 = PCNT overflow interrupts are disabled
1 = Interrupts are generated each time PCNT rolls over to $0000
PACTL — Pulse Accumulator Control
$1026
BIT 7
654321
BIT 0
—
PAEN
PAMOD
PEDGE
—
I4/O5
RTR1
RTR0
RESET:
00000000
EA9 PLS ACC BLOCK
PEDGE
PAMOD
PAEN
PACTL CONTROL
INTERNAL
DATA BUS
PACNT 8-BIT COUNTER
PA7/
PAI/
OC1
INTERRUPT
REQUESTS
PAIF
PAOVF
TFLG2 INTERRUPT STATUS
PAOVI
PAII
PAOVF
PAOVI
PAIF
PAII
TMSK2 INT ENABLES
1
2
OVERFLOW
ENABLE
DISABLE
FLAG SETTING
CLOCK
PAI EDGE
PAEN
2
:1
MUX
OUTPUT
BUFFER
INPUT BUFFER
AND
EDGE DETECTOR
FROM
MAIN TIMER OC1
DATA
BUS
MCU PIN
PLLTO
÷ 64 CLOCK *
(FROM MAIN TIMER)
FROM DATA DIRECTION
BIT FOR PORT A PIN 7
* REFER TO TIMER AND PLL BLOCK DIAGRAMS.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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