參數(shù)資料
型號: MC68HC11D0CFN2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 5/138頁
文件大?。?/td> 1047K
代理商: MC68HC11D0CFN2
Programmable Timer
MC68HC711D3 Data Sheet, Rev. 2.1
102
Freescale Semiconductor
8.7.1 Pulse Accumulator Control Register
Four of the pulse accumulator control register (PACTL) bits control an 8-bit pulse accumulator system.
Another bit enables either the OC5 function or the IC4 function, while two other bits select the rate for the
real-time interrupt system.
DDRA7 — Data Direction Control for Port A Bit 7
The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also be used as
general-purpose I/O or as an output compare.
NOTE
Even when port A bit 7 is configured as an output, the pin still drives the
input to the pulse accumulator.
Refer to Chapter 5 Input/Output (I/O) Ports for more information.
PAEN — Pulse Accumulator System Enable Bit
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode Bit
0 = Event counter
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control Bit
This bit has different meanings depending on the state of the PAMOD bit, as shown in Table 8-8.
DDRA3 — Data Direction Register for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare 5 Bit
RTR1 and RTR0 — RTI Interrupt Rate Select Bits
Address:
$0026
Bit 7
654321
Bit 0
Read:
DDRA7
PAEN
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
Write:
Reset:
00000000
Figure 8-20. Pulse Accumulator Control Register (PACTL)
Table 8-8. Pulse Accumulator Edge Control
PAMOD
PEDGE
Action on Clock
0
PAI falling edge increments the counter.
0
1
PAI rising edge increments the counter.
1
0
A 0 on PAI inhibits counting.
1
A 1 on PAI inhibits counting.
相關(guān)PDF資料
PDF描述
MC68HC11D0CFB2 8-BIT, 2 MHz, MICROCONTROLLER, PQFP44
MC68HC11D3CFN2 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC44
MC68HC711D3CP3 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP40
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC11D0CFN3 制造商: 功能描述: 制造商:undefined 功能描述:
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