參數(shù)資料
型號: MC68HC11D0CFB2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 136/138頁
文件大?。?/td> 1047K
代理商: MC68HC11D0CFB2
Output Compare (OC)
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
97
PR1 and PR0 — Timer Prescaler Select Bits
These bits are used to select the prescaler divide-by ratio. In normal modes, PR1 and PR0 can be
written once only, and the write must be within 64 cycles after reset. Refer to Table 8-4 for specific
timing values.
8.4.10 Timer Interrupt Flag 2 Register
The timer interrupt flag 2 register (TFLG2) bits indicate when certain timer system events have occurred.
Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate
in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same
position.
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time (Periodic) Interrupt Flag
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits 3–0 — Not implemented
Always read 0.
Table 8-4. Timer Prescale
PR1 and PR0
Prescaler
0 0
1
0 1
4
1 0
8
1 1
16
Address:
$0025
Bit 7
654321
Bit 0
Read:
TOF
RTIF
PAOVF
PAIF
0000
Write:
Reset:
00000000
Figure 8-15. Timer Interrupt Flag 2 Register (TFLG2)
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