參數(shù)資料
型號(hào): MC68HC08QY2CDTE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝: 0.65 MM PITCH, LEAD FREE, TSSOP-16
文件頁數(shù): 126/176頁
文件大小: 1124K
代理商: MC68HC08QY2CDTE
Functional Description
MC68HC08QY/QT Family Data Sheet, Rev. 2
Freescale Semiconductor
53
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module.
1 = LVI module power disabled
0 = LVI module power enabled
LVITRIP — LVI Trip Point Selection Bit
LVITRIP selects the voltage operating mode of the LVI module. The voltage mode selected for the LVI
should match the operating VDD for the LVI’s voltage trip points for each of the modes.
1 = LVI operates for a 5-V protection
0 = LVI operates for a 2-V protection
NOTE
The LVITRIP bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096
BUSCLKX4 cycle delay.
1 = Stop mode recovery after 32 BUSCLKX4 cycles
0 = Stop mode recovery after 4096 BUSCLKX4 cycles
NOTE
Exiting stop mode by an LVI reset will result in the long stop recovery.
When using the LVI during normal operation but disabling during stop mode, the LVI will have an
enable time of tEN. The system stabilization time for power-on reset and long stop recovery (both 4096
BUSCLKX4 cycles) gives a delay longer than the LVI enable time for these startup scenarios. There
is no period where the MCU is not protected from a low-power condition. However, when using the
short stop recovery configuration option, the 32 BUSCLKX4 delay must be greater than the LVI’s turn
on time to avoid a period in startup where the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
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