- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45242 > MC68HC08KX8P (FREESCALE SEMICONDUCTOR INC) 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP16 PDF資料下載
參數(shù)資料
| 型號： | MC68HC08KX8P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 28/210頁 |
| 文件大?。?/td> | 1346K |
| 代理商： | MC68HC08KX8P |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁
Functional Description
MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
123
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is
12.4.3.6 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems,
the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are disabled.
Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the
receiver out of the standby state:
1.
Address mark — An address mark is a 1 in the most significant bit position of a received character.
When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing
the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can then
compare the character containing the address mark to the user-defined address of the receiver. If
they are the same, the receiver remains awake and processes the characters that follow. If they
are not the same, software can set the RWU bit and put the receiver back into the standby state.
2.
Idle input line condition — When the WAKE bit is clear, an idle character on the RxD pin wakes the
receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver
does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit,
ILTY, determines whether the receiver begins counting 1s as idle character bits after the start bit
or after the stop bit.
NOTE
With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
12.4.3.7 Receiver Interrupts
These sources can generate CPU interrupt requests from the SCI receiver:
SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has
transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting
the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver
CPU interrupts.
Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive 1s shifted in from the
RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate CPU
interrupt requests.
12.4.3.8 Error Interrupts
These receiver error flags in SCS1 can generate CPU interrupt requests:
Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new
character before the previous character was read from the SCDR. The previous character remains
in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3
enables OR to generate SCI error CPU interrupt requests.
170
176
–
170
--------------------------
100
×
3.53%.
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC908KX8VP | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP16 |
| MC68HC908KX8CDW | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16 |
| MC68HC908LK24CFQ | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| MC68HC908LK24CFU | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| MC68HC908LK24CPK | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC08LJ12 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Addendum to MC68HC908LJ12 Technical Data |
| MC68HC08LJ12CFB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Addendum to MC68HC908LJ12 Technical Data |
| MC68HC08LJ12CFU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Addendum to MC68HC908LJ12 Technical Data |
| MC68HC08LJ12CPB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:low-voltage version of the MC68HC908LJ12 |
| MC68HC08LN56 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。