Memory Map
Technical Data
MC68HC08AZ32A — Rev 1.0
46
Memory Map
MOTOROLA
$0014
SCI Control Register 2
(SCC2)
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R: LVISTOP ROMSEC LVIRST
W:
R
R:
TOF
TOIE
W:
0
R;
0
W:
R:
Bit 15
W;
R
R:
Bit 7
W:
R
R:
Bit 15
W:
R:
Bit 7
W:
R:
CH0F
CH0IE
W:
0
R:
Bit 15
W:
R:
Bit 7
W:
R:
CH1F
CH1IE
W:
0
R:
Bit 15
W:
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
$0015
SCI Control Register 3
(SCC3)
R8
T8
R
R
ORIE
NEIE
FEIE
PEIE
$0016
SCI Status Register 1 (SCS1)
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
$0017
SCI Status Register 2 (SCS2)
0
0
0
0
0
0
BKF
RPF
$0018
SCI Data Register (SCDR)
R7
T7
0
R6
T6
0
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
$0019
SCI Baud Rate Register
(SCBR)
SCP1
SCP0
R
SCR2
SCR1
SCR0
$001A
IRQ Status and Control
Register (ISCR)
Keyboard Status/Control
0
R
0
0
R
0
0
R
0
0
R
0
IRQF
R
KEYF
0
IMASK
MODE
ACK
0
ACKK
1
$001B
(KBSCR)
IMASKK MODEK
$001C
PLL Control Register (PCTL)
PLLIE
PLLF
PLLON
BCS
1
1
1
$001D
PLL Bandwidth Control
Register (PBWC)
PLL Programming Register
AUTO
LOCK
ACQ
XLD
0
0
0
0
$001E
(PPG)
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
$001F
Mask Option Register A
(MORA)
LVIPWR
R
0
TRST
SSREC
R
0
R
COPRS
R
STOP
R
COPD
R
R
R
$0020
Timer A Status and Control
Register (TASC)
Keyboard Interrupt Enable
Register (KBIER)
Timer A Counter Register
High (TACNTH)
Timer A Counter Register
Low (TACNTL)
Timer A Modulo Register
High (TAMODH)
$0025
Timer A Modulo Register Low
TSTOP
PS2
PS1
PS0
$0021
0
0
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
$0022
14
R
6
R
13
R
5
R
12
R
4
R
11
R
3
R
10
R
2
R
9
R
1
R
Bit 8
R
Bit 0
R
$0023
$0024
14
13
12
11
10
9
Bit 8
(TAMODL)
6
5
4
3
2
1
Bit 0
$0026
Timer A Channel 0 Status and
Control Register (TASC0)
Timer A Channel 0 Register
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
$0027
High (TACH0H)
14
13
12
11
10
9
Bit 8
$0028
Timer A Channel 0 Register
Low (TACH0L)
$0029
Timer A Channel 1 Status and
Control Register (TASC1)
Timer A Channel 1 Register
6
5
4
3
2
1
Bit 0
0
R
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
$002A
High (TACH1H)
14
13
12
11
10
9
Bit 8
Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
R
= Reserved
Figure 2-2. I/O Data, Status and Control Registers (Sheet 2 of 4)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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