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參數(shù)資料
| 型號(hào)： | MC68HC05SU3AB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁(yè)數(shù)： | 48/80頁(yè) |
| 文件大小： | 710K |
| 代理商： | MC68HC05SU3AB |
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MOTOROLA
7-6
MC68HC05SU3A
CPU CORE AND INSTRUCTION SET
7
Table 7-3 Branch instructions
Relative addressing mode
Function
Mnemonic
Opcode
# Bytes # Cycles
Branch always
BRA
20
2
3
Branch never
BRN
21
2
3
Branch if higher
BHI
22
2
3
Branch if lower or same
BLS
23
2
3
Branch if carry clear
BCC
24
2
3
(Branch if higher or same)
(BHS)
24
2
3
Branch if carry set
BCS
25
2
3
(Branch if lower)
(BLO)
25
2
3
Branch if not equal
BNE
26
2
3
Branch if equal
BEQ
27
2
3
Branch if half carry clear
BHCC
28
2
3
Branch if half carry set
BHCS
29
2
3
Branch if plus
BPL
2A
2
3
Branch if minus
BMI
2B
2
3
Branch if interrupt mask bit is clear
BMC
2C
2
3
Branch if interrupt mask bit is set
BMS
2D
2
3
Branch if interrupt line is low
BIL
2E
2
3
Branch if interrupt line is high
BIH
2F
2
3
Branch to subroutine
BSR
AD
2
6
Table 7-4 Bit manipulation instructions
Addressing modes
Bit set/clear
Bit test and branch
Function
Mnemonic
Opcode
# Bytes # Cycles
Opcode
# Bytes # Cycles
Branch if bit n is set
BRSET n (n=0–7)
2n
3
5
Branch if bit n is clear
BRCLR n (n=0–7)
01+2n
3
5
Set bit n
BSET n (n=0–7)
10+2n
2
5
Clear bit n
BCLR n (n=0–7)
11+2n
2
5
TPG
50
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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