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參數(shù)資料
| 型號： | MC68HC05SU3AB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 40/80頁 |
| 文件大?。?/td> | 710K |
| 代理商： | MC68HC05SU3AB |
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MC68HC05SU3A
MOTOROLA
6-3
TIMER
6
6.2
Timer Control Register (TCR)
The TCR enables the software to control the operation of the timer.
TIF — Timer Interrupt Flag
1 (set)
–
The timer has reached a count of zero.
0 (clear) –
The timer has not reached a count of zero.
The timer interrupt ag is set when the 8-bit counter decrements to zero. This bit is cleared on
reset, or by writing a “0” to the TIF bit.
TIM — Timer Interrupt Mask
1 (set)
–
Timer interrupt request to the CPU is masked (disabled).
0 (clear) –
Timer interrupt request to the CPU is not masked (enabled).
A reset sets this bit to one; it must then be cleared by software to enable the timer interrupt to the
CPU. This timer interrupt mask only masks timer interrupt request to the CPU, and does not affect
counting of the 8-bit counter or the setting of TIF.
TCEX — Timer Clock EXternal
TINE — Timer INput Enable
These two bits selects the source of the timer clock. Reset or power-on clears these bits to zero.
PRER — PREscaler Reset
Writing a “1” to this write-only bit will reset the prescaler to zero, which is necessary for any new
counts set by writing to the Timer Data Register.This bit always reads as zero, and is not affected
by reset.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$09
TIF
TIM
TCEX
TINE
PRER
PRE2
PRE1
PRE0
0100 -100
TCEX
TINE
Clock Source
00
Internal clock to timer
01
“AND” of internal clock and TIMER pin to timer
10
Input clock to timer disabled
11
TIMER pin to timer
TPG
43
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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