參數(shù)資料
型號: MC68HC05C9EP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝: PLASTIC, DIP-40
文件頁數(shù): 138/144頁
文件大?。?/td> 1628K
代理商: MC68HC05C9EP
Serial Peripheral Interface (SPI)
Functional Description
MC68HC05C9E
Advance Information
MOTOROLA
Serial Peripheral Interface (SPI)
93
N
O
N-D
I
SC
L
O
SU
R
E
AG
R
EEMENT
R
E
Q
U
IR
ED
10.5 Functional Description
Figure 10-2 shows a block diagram of the serial peripheral interface
circuitry. When a master device transmits data to a slave via the MOSI
line, the slave device responds by sending data to the master device via
the master’s MISO line. This implies full duplex transmission with both
data out and data in synchronized with the same clock signal. Thus, the
byte transmitted is replaced by the byte received and eliminates the
need for separate transmit-empty and receive-full status bits. A single
status bit (SPIF) is used to signify that the input/output (I/O) operation
has been completed.
Figure 10-2. Serial Peripheral Interface Block Diagram
S
6
7
543210
SPE
SPIE
SPI CONTROL REGISTER (SPCR)
MSTR
CPOL
CPHA
SPR1
SPR2
$000A
WCOL
SPIF
SPI STATUS REGISTER (SPSR)
0
MODF
0
$000B
BIT 6
BIT 7
SPI DATA REGISTER (SPDR)
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
$000C
DWOM
00
SPI SHIFT REGISTER
DIVIDER
CLOCK
LOGIC
SPDR ($000C)
7 6 5 4 3 2 1 0
MODF
WCOL
SPIF
SPR1
SPR0
CPOL
CPHA
MSTR
SPE
SPIE
PD3/
MOSI
PD2/
MISO
÷ 2
÷ 32
÷ 16
÷ 4
SELECT
SPI
CONTROL
INTERNAL DATA BUS
MSTR
S
M
INTERNAL
CLOCK
(XTAL
÷2)
SPI CLOCK (MASTER)
SPI INTERRUPT REQUEST
SH
IF
T
C
L
OC
K
PD4/
SCK
PD5/
SS
SLAVE
SPI
MASTER
CLOCK
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