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參數(shù)資料
| 型號(hào)： | MC68HC05C9AFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 94/160頁(yè) |
| 文件大?。?/td> | 4128K |
| 代理商： | MC68HC05C9AFN |
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Interrupts
Non-Maskable Software Interrupt (SWI)
MC68HC05C9A — Rev. 4.0
General Release Specification
Interrupts
NON-DISCLOSURE
AGREEMENT
REQUIRED
4.3 Non-Maskable Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt: It is
executed regardless of the state of the I bit in the CCR. If the I bit is zero
(interrupts enabled), SWI executes after interrupts which were pending
when the SWI was fetched, but before interrupts generated after the SWI
was fetched. The interrupt service routine address is specified by the
contents of memory locations $3FFC and $3FFD.
4.4 External Interrupt (IRQ or Port B)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
IRQ. It is then synchronized internally and serviced as specified by the
contents of $3FFA and $3FFB.
When any of the port B pullups are enabled, each pin becomes an
additional external interrupt source which is executed identically to the
IRQ pin. Port B interrupts follow the same edge/edge-level selection as
the IRQ pin. The branch instructions BIL and BIH also respond to the
port B interrupts in the same way as the IRQ pin. See 7.4 Port B.
Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-
only trigger operation is selectable. The sensitivity is software-controlled
by the IRQ bit in the option register ($3FDF).
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse can be latched
and serviced as soon as the I bit is cleared.
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For More Information On This Product,
Go to: www.freescale.com
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