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參數(shù)資料
| 型號(hào)： | MC68EZ328 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Integrated Portable System Processor |
| 中文描述： | 集成便攜式系統(tǒng)處理器 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 103K |
| 代理商： | MC68EZ328 |
Parallel General-Purpose I/O Ports
DRAM Controller
5
interrupt service routine of a lower priority interrupt may be suspended by a higher priority interrupt
request. The on-chip interrupt controller has the following major features:
Prioritized Interrupt Sources (Internal and External)
A Fully Nested Interrupt Environment
Programmable Vector Generation
Interrupt Masking
Wake-up interrupt Masking
2.6
Parallel General-Purpose I/O Ports
The MC68EZ328 supports up to 54-bit general-purpose I/O ports, which can be configured as general-
purpose I/O pins or as dedicated peripheral interface pins of the on-chip modules. Each port pin can be
independently programmed as general-purpose I/O pin, while other pins related to the same on-chip
peripheral can be used as dedicated pins. Even all the pins for a particular peripheral are configured as
general-purpose I/O, the peripheral will still operate normally, although this is only useful in the case of the
RTC and timer modules.
2.7
Low-Power Stop Logic
Various options for power-saving are available: turning off unused peripherals, reducing processor clock
speed, disabling the processor altogether, or a combination of these.
A wake-up from low-power mode can be achieved by causing an interrupt at the interrupt controller logic
which runs throughout the period of processor low-power. Selectable interrupt will cause a wake-up of the
68EC000 core. The on-chip peripherals can initiate a wake-up; for example, the timer can be set to wake
up after a certain elapsed time, or number of external events.
3
DRAM Controller
In order to provide more flexibility for system designers, the MC68EZ328 support a glueless interface to
8-bit or 16 bit DRAM. This DRAM controller supports up to two banks of DRAM/EDO DRAM with each
bank up to 512kx8, 256kx16,1Mx16, or 8Mx8. In addition, CAS-before-RAS refresh cycles and Self-
Refresh mode DRAM are also supported.
4
UART and Infra-red Communication Support
The UART supports standard asynchronous serial communications at normal baud rates and is compatible
with IrDA 1.0 Physical Communication Protocol with up to 115.2 Kbps.
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