- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨�(m菐i)璩�(m脿i)IC缍�(w菐ng) > PDF鐩寗4051 > MC68EC040FE25A (Freescale Semiconductor)IC MPU 32BIT 25MHZ 184-CQFP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MC68EC040FE25A |
| 寤�(ch菐ng)鍟嗭細 | Freescale Semiconductor |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 319/442闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MPU 32BIT 25MHZ 184-CQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 24 |
| 绯诲垪锛� | M680x0 |
| 铏曠悊鍣ㄩ(l猫i)鍨嬶細 | M680x0 32-浣� |
| 閫熷害锛� | 25MHz |
| 闆诲锛� | 5V |
| 瀹夎椤�(l猫i)鍨嬶細 | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 184-BCQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 184-CQFP锛�31.3x31.3锛� |
| 鍖呰锛� | 鎵樼洡(p谩n) |
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B-10
M68040 USER鈥橲 MANUAL
MOTOROLA
MC68EC040 REV2.3 (01/31/2000)
direct addressing modes, this field is $0. The saved PC value is the logical address of
the instruction that follows the unimplemented floating-point instruction. This value will
be restored during RTE execution. The vector offset format number ($4) is used for
this eight-word stack frame. Note that an MC68040 cannot correctly handle a stack for-
mat $4. The PC of the faulted instruction contains a long-word PC of the floating-point
instruction that caused the trap to occur. The information is provided so that the in-
struction is available for software emulation of floating-point instructions. The proces-
sor generates exception vector number 11 for the unimplemented F-line instruction
exception vector, fetches the address of the F-line exception handler from the excep-
tion vector table, and begins execution of the handler after prefetching instructions to
fill the pipeline. Refer to Section 8 Exception Processing for details about exception
processing.
B.5.2 MC68EC040 Stack Frames
When the processor executes an RTE instruction, it examines the stack frame on top of the
active supervisor stack to determine if it is a valid frame and what type of context restoration
it requires. The set of stack frames included for exception processing are four- and six-word
stack frames, a four-word throwaway stack frame, an access error stack frame, and a new
eight-word unimplemented oating-point stack frame. The stack frame that the MC68040
can generate and the MC68EC040 can process is the oating-point post-instruction stack
frame. Refer to Section 8 Exception Processing for details about exception stack frames.
When the MC68EC040 writes or reads a stack frame, it uses long-word operand transfers
wherever possible. Using a long-word-aligned stack pointer greatly enhances exception pro-
cessing performance. The processor does not necessarily read or write the stack frame data
in sequential order. The system software should not depend on a particular exception gen-
erating a particular stack frame. For compatibility with future devices, the software should be
able to handle any type of stack frame for any type of exception. The MC68EC040 does not
generate the oating-point post-instruction stack frame. The MC68040 cannot accept the
eight-word unimplemented stack frame. The MC68EC040 can handle all MC68040 stack
frame formats.
B.6 SOFTWARE CONSIDERATIONS
The following MC68EC040 instructions are different from the MC68040: PTEST, PFLUSH,
CPUSH, CINV, MOVEC, and all oating-point instructions.
Eight-Word Stack Frame (Format $4)
Stack Frames
Exception Types
Stacked PC Points To
The MC68040 cannot
generate or read this stack.
Effective address field is
the address of the faulted
instruction operand.
15
0
SP
+$02
+$06
+$08
+$0C
STATUS REGISTER
PROGRAM COUNTER
0100
VECTOR OFFSET
EFFECTIVE ADDRESS
PC OF FAULTED
INSTRUCTION
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For More Information On This Product,
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| MC68EC040FE25B | 鍒堕€犲晢:MOTOROLA 鍒堕€犲晢鍏ㄧū(ch膿ng):Motorola, Inc 鍔熻兘鎻忚堪:M68000-compatible, high-performance, 32-bit microprocessors |
| MC68EC040FE33A | 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B W/ CACHE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤�(l猫i)鍨�:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324 |
| MC68EC040FE33B | 鍒堕€犲晢:MOTOROLA 鍒堕€犲晢鍏ㄧū(ch膿ng):Motorola, Inc 鍔熻兘鎻忚堪:M68000-compatible, high-performance, 32-bit microprocessors |
| MC68EC040FE40A | 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B W/ CACHE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤�(l猫i)鍨�:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324 |
| MC68EC040RC20A | 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B W/ CACHE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤�(l猫i)鍨�:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324 |
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