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鍨嬭櫉锛� MC68EC040FE25A
寤犲晢锛� Freescale Semiconductor
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鎻忚堪锛� IC MPU 32BIT 25MHZ 184-CQFP
妯欐簴鍖呰锛� 24
绯诲垪锛� M680x0
铏曠悊鍣ㄩ鍨嬶細 M680x0 32-浣�
閫熷害锛� 25MHz
闆诲锛� 5V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 184-BCQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 184-CQFP锛�31.3x31.3锛�
鍖呰锛� 鎵樼洡
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MOTOROLA
M68040 USER鈥橲 MANUAL
A-5
MC68LC040 REV2.3 (01/29/2000)
A.2 INTERRUPT PRIORITY LEVEL (IPL2鈥揑PL0)
The IPL2鈥揑PL0 pins do not have any affect on the selection of output buffer impedance.
A.3 JTAG SCAN (JS0)
The MC68040 DLE pin name has been changed to JS0. During normal operation, the JS0
pin cannot oat, it must be tied to GND or Vcc directly or through a resistor. During board
testing, this pin retains the functionality of the JTAG scan of the MC68040 for compatibility
purposes. Refer to Section 6 IEEE 1149.1A Test Access Port (JTAG) for details concern-
ing IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture.
A.4 DATA LATCH AND MULTIPLEXED BUS MODES
The MC68LC040 does not implement the data latch or multiplexed modes of operation. The
CDIS pin is ignored at the rising edge of reset. All timing and drive capabilities of the
MC68LC040 are equivalent to those of the MC68040 in small output buffer impedance
mode.
A.5 FLOATING-POINT UNIT (FPU)
The FPU is not implemented on the MC68LC040. All oating-point instructions cause an
unimplemented oating-point exception to be taken with a new eight-word stack frame (for-
mat $4). The stack frame contains the status register (SR), program counter (PC), vector off-
set, effective address of the operand (where applicable), and PC value of the
unimplemented oating-point instruction.
A.5.1 Unimplemented Floating-Point Instructions and Exceptions
All legal MC68040 and MC68881/MC68882 oating-point instructions are dened as unim-
plemented oating-point instructions on the MC68LC040. These instructions generate a for-
mat $4 stack frame during exception processing before taking an F-line exception. These
instructions trap as an F-line exception, and the F-line exception handler can emulate them
in software to maintain user-object-code compatibility.
The MC68LC040 assists the emulation process by distinguishing unimplemented oat-
ing-point instructions from other unimplemented F-line instructions. To aid emulation, the
effective address is calculated and saved in the format $4 stack frame. This simplies and
speeds up the emulation process by eliminating the need for the emulation routine to deter-
mine the effective address and by providing information required to emulate the instruction
on the exception stack frame in the supervisor address space. However, the oating-point
instruction can reside in user space; therefore, the oating-point unimplemented exception
handler may need to access user instruction space. The following processing steps occur
for an unimplemented oating-point instruction:
1. When an unimplemented floating-point instruction is encountered, the instruction is
partially decoded, and the effective address is calculated, if required.
2. The processor waits for all previous integer instructions, write-backs, and associated
exception processing to complete before beginning exception processing for the un-
implemented floating-point instruction. Any access error that occurs in completing the
write-backs causes an access error exception, and the resulting stack frame indicates
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC68EC040FE25B 鍒堕€犲晢:MOTOROLA 鍒堕€犲晢鍏ㄧū:Motorola, Inc 鍔熻兘鎻忚堪:M68000-compatible, high-performance, 32-bit microprocessors
MC68EC040FE33A 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B W/ CACHE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
MC68EC040FE33B 鍒堕€犲晢:MOTOROLA 鍒堕€犲晢鍏ㄧū:Motorola, Inc 鍔熻兘鎻忚堪:M68000-compatible, high-performance, 32-bit microprocessors
MC68EC040FE40A 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B W/ CACHE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
MC68EC040RC20A 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B W/ CACHE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-324