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參數(shù)資料
| 型號(hào)： | MC68711D3CFBE2 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 94/124頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 44-QFP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 系列： | HC11 |
| 核心處理器： | HC11 |
| 芯體尺寸： | 8-位 |
| 速度： | 2MHz |
| 連通性： | SCI，SPI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲(chǔ)器容量： | 4KB（4K x 8） |
| 程序存儲(chǔ)器類型： | OTP |
| RAM 容量： | 192 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-QFP |
| 包裝： | 托盤 |
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SERIAL COMMUNICATIONS INTERFACE
TECHNICAL DATA
7-5
7.5 SCI Error Detection
Three error conditions, SCDR overrun, received bit noise, and framing can occur dur-
ing generation of SCI system interrupts. Three bits (OR, NF, and FE) in the serial com-
munications status register (SCSR) indicate if one of these error conditions exists. The
overrun error (OR) bit is set when the next byte is ready to be transferred from the re-
ceive shift register to the SCDR and the SCDR is already full (RDRF bit is set). When
an overrun error occurs, the data that caused the overrun is lost and the data that was
already in SCDR is not disturbed. The OR is cleared when the SCSR is read (with OR
set), followed by a read of the SCDR.
The noise flag (NF) bit is set if there is noise on any of the received bits, including the
start and stop bits. The NF bit is not set until the RDRF flag is set. The NF bit is cleared
when the SCSR is read (with FE equal to one) followed by a read of the SCDR.
When no stop bit is detected in the received data character, the framing error (FE) bit
is set. FE is set at the same time as the RDRF. If the byte received causes both fram-
ing and overrun errors, the processor only recognizes the overrun error. The framing
error flag inhibits further transfer of data into the SCDR until it is cleared. The FE bit is
cleared when the SCSR is read (with FE equal to one) followed by a read of the SCDR.
7.6 SCI Registers
There are five addressable registers in the SCI.
7.6.1 Serial Communications Data Register (SCDR)
SCDR is a parallel register that performs two functions. It is the receive data register
when it is read, and the transmit data register when it is written. Reads access the re-
ceive data buffer and writes access the transmit data buffer. Receive and transmit are
double buffered.
*U = Unaffected
7.6.2 Serial Communications Control Register 1 (SCCR1)
The SCCR1 register provides the control bits that determine word length and select
the method used for the wake-up feature.
R8 — Receive Data Bit 8
If M bit is set, R8 stores the ninth bit in the receive data character.
SCDR — SCI Data Register
$002F
Bit 7
654321
Bit 0
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
RESET:
U*
UUUUUUU
SCCR1 — SCI Control Register 1
$002C
Bit 7
654321
Bit 0
R8
T8
0
M
WAKE
0
RESET:
U
000000
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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