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| 型號： | MC68331MEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 31/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 16MHZ 132-PQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | M683xx |
| 核心處理器： | CPU32 |
| 芯體尺寸： | 32-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 18 |
| 程序存儲器類型： | ROMless |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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MC68331TS/D
37
3.7 Resets
Reset procedures handle system initialization and recovery from catastrophic failure. The MCU per-
forms resets with a combination of hardware and software. The system integration module determines
whether a reset is valid, asserts control signals, performs basic system configuration based on hard-
ware mode-select inputs, then passes control to the CPU.
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM. Resets are gated
by the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchronous reset
can occur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. If there
is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are clocked in
order to allow completion of write cycles in progress at the time RESET is asserted.
Reset is the highest-priority CPU32 exception. Any processing in progress is aborted by the reset ex-
ception, and cannot be restarted. Only essential tasks are performed during reset exception processing.
Other initialization tasks must be accomplished by the exception handler routine.
3.7.1 SIM Reset Mode Selection
The logic states of certain data bus pins during reset determine SIM operating configuration. In addition,
the state of the MODCLK pin determines system clock source and the state of the BKPT pin determines
what happens during subsequent breakpoint assertions. The following table is a summary of reset
mode selection options.
3.7.2 Functions of Pins for Other Modules During Reset
Generally, pins associated with modules other than the SIM default to port functions, and input/output
ports are set to input state. This is accomplished by disabling pin functions in the appropriate control
registers, and by clearing the appropriate port data direction registers. Refer to individual module sec-
tions in this manual for more information. The following table is a summary of module pin function out
of reset.
Table 18 Reset Mode Selection
Mode Select Pin
Default Function
(Pin Left High)
Alternate Function
(Pin Pulled Low)
DATA0
CSBOOT 16-Bit
CSBOOT 8-Bit
DATA1
CS0
CS1
CS2
BR
BG
BGACK
DATA2
CS3
CS4
CS5
FC0
FC1
FC2
DATA3
DATA4
DATA5
DATA6
DATA7
CS6
CS[7:6]
CS[8:6]
CS[9:6]
CS[10:6]
ADDR19
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
DATA8
DSACK0, DSACK1,
AVEC, DS, AS,
SIZ[1:0]
PORTE
DATA9
IRQ[7:1]
MODCLK
PORTF
DATA11
Test Mode Disabled
Test Mode Enabled
MODCLK
VCO = System Clock
EXTAL = System Clock
BKPT
Background Mode Disabled
Background Mode Enabled
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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