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MOTOROLA
D-42
REGISTER SUMMARY
MC68331
USER’S MANUAL
D
PCLKS
PCS[3:0]
PE
PE[7:0]
PEDGE
PEPA[7:0]
PF
PF[7:0]
PFPA[7:0]
PORTGP[7:0]
PIRQL[2:0]
PITM[7:0]
PIV[7:0]
POW
PPROUT
PPR[2:0]
PQS[7:0]
PQSPA[6:0]
PT
PTP
RAF
RDRF
RE
RIE
RR[0:F]
RSTEN
R/W
RWU
R[8:0]/T[8:0]
S
SBK
SCBR
SFA
SFB
SHEN[1:0]
SLIMP
SLOCK
SLVEN
SPACE
SPBR
SPE
SPIF
SPIFIE
STEXT
STOP
STOP
STOPP
STRB
PCLK Pin State (Read Only)
Peripheral Chip Select
Parity Enable
Port E Data
Pulse Accumulator Edge Control
Port E Pin Assignment
Parity Error
Port F Data
Port F Pin Assignment
Port GP Data
Periodic Interrupt Request Level
Periodic Interrupt Timing Modulus
Periodic Interrupt Vector
Power-Up Reset
PWM Clock Output Enable
PWM Prescaler/PCLK Select
Port QS Data
Port QS Pin Assignment
Parity Type
Periodic Timer Prescaler Control
Receiver Active
Receive Data Register Full
Receiver Enable
Receiver Interrupt Enable
Receive Data RAM
Reset Enable
Read/Write
Receiver Wakeup
SCI Receive/Transmit Data
Supervisor/User State
Send Break
SCI Baud Rate
PWMA Slow/Fast Select
PWMB Slow/Fast Select
Show Cycle Enable
LIMP Mode
Synthesizer Lock
Factory Test Mode Enabled
Address Space Select
Serial Clock Baud Rate
QSPI Enable
QSPI Finished Flag
SPI Finished Interrupt Enable
Stop Mode External Clock
Stop Clocks
Stop Enable
Stop Prescaler
Address Strobe/Data Strobe
PACNT
CR[0:F]
SCCR1
PORTE
PACNT
PEPAR
SCSR
PORTF
PFPAR
PORTGP
PICR
PITR
PICR
RSR
PWMC
PWMC
PORTQS
PQSPAR
SCCR1
PITR
SCSR
SCSR
SCCR1
SCCR1
QSPI RAM
SYNCR
CSOR[0:10], CSORBT
SCCR1
SCDR
SR
SCCR1
SCCR0
PWMC
PWMC
SIMCR
SYNCR
SYNCR
SIMCR
CSOR[0:10], CSORBT
SPCR0
SPCR1
SPSR
SPCR2
SYNCR
GPTMCR
QSMCR
GPTMCR
CSOR[0:10], CSORBT
Table D-18 Register Bit and Field Mnemonics, (Continued)
Mnemonic
Name
Register Location